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參數(shù)資料
| 型號： | 5962-9457501QEA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, CDIP16 |
| 封裝： | DIP-16 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 239K |
| 代理商： | 5962-9457501QEA |
4
UCC1806
UCC2806
UCC3806
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = –55°C to +125°C for the
UCC1806,
40°C to +85°C for the UCC2806, and 0°C to +70°C for the UCC3806; VIN = 12V, RT = 33k, CT = 330pF,
CBYPASS on VREF = 0.01F, TA = TJ.
PARAMETER
TEST CONDITION
UCC1806 / UCC2806
UCC3806
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Output Section
Output Supply Voltage
2.5
15
2.5
15
V
Output Low Level
ISINK = 20mA
100
300
100
200
mV
ISINK = 100mA
0.40
1.1
0.40
1.1
V
Output High Level
ISOURCE = 20mA
11.6
11.9
11.6
11.9
V
ISOURCE = 100mA
11
11.6
11
11.6
V
Rise Time
TJ = 25°C, CLOAD = 1000pF
35
65
35
65
ns
Fall Time
TJ = 25°C, CLOAD = 1000pF
35
65
35
65
ns
Under Voltage Lockout Section
Startup Current
VIN < Start Threshold
50
100
50
100
A
Operating Supply Current
1
1.4
1
1.4
mA
VIN Shunt Voltage
IVIN = 10mA
15
17.5
15
17.5
V
Startup Threshold
6.5
7.5
8
6.5
7.5
8
V
Threshold Hysteresis
0.75
V
Note 1: All voltages are with respect to Ground, Pin 12.
Note 2: Currents are positive into, negative out of the specified terminal.
Note 3: Parameters measured at trip point of latch with VPIN 5 = VREF , VPIN 6 = 0V.
Note 4: Amplifier gain defined as: G = delta change at Pin 7/delta change forced at Pin 4 delta voltage at Pin 4 = 0 to 1V.
Note 5: Guaranteed by design. Not 100% tested in production.
Note 6: Current Sense Amp output is slew rate limited to provide noise immunity.
Note 7: Line Range = 10V to 15V, Load Range = 0.2mA to 5mA.
PIN DESCRIPTIONS
AOUT and BOUT: AOUT and BOUT provide alternating
high current gate drive for the external MOSFETs. Duty
cycle can be varied from 0 to 50% where minimum dead
time is a function of CT. Both outputs use MOS transistor
switches with inherent anti-parallel body diodes to clamp
voltage swings to the supply rails, allowing operation
without the use of clamp diodes.
COMP: COMP is the output of the error amplifier and the
input of the PWM comparator. The error amplifier is a low
output impedance, 2MHz operational amplifier which al-
lows sinking or sourcing of current at the COMP pin. The
error amplifier is internally current limited, so that zero
duty cycle can be commanded by externally forcing
COMP to GND.
CS–: CS- is the inverting input of the 3X, differential cur-
rent sense amplifier.
CS+: CS+ is the non-inverting input of the 3X, differential
current sense amplifier.
CT: CT is the oscillator timing capacitor connection point,
which is charged by the current set by RT. CT is dis-
charged to GND through a 2.6mA current sink. This
causes a linear discharge of CT to zero volts which then
initiates the next switching cycle. Dead time occurs dur-
ing the discharge of CT, forcing AOUT and BOUT low.
Switching frequency (fs) and dead time (td) are approxi-
mated by:
fs
RT
CT
td
and td
CT
=
+
=
1
2
961
CURLIM: CURLIM programs the primary current limit
threshold and determines whether the device will latch
off or retry after an overcurrent condition. When a shut-
down signal is generated, a 200
A current source to
ground pulls down on CURLIM. If the voltage on the pin
remains above 350mV the device remains latched and
the power must be cycled to restart. If the voltage on the
pin falls below 350mV, the device attempts a restart. The
voltage threshold is typically set by a resistor divider from
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