Vishay Siliconix
DG408, DG409
Document Number: 70062
S10-0934-Rev. H, 19-Apr-10
www.vishay.com
1
8-Ch/Dual 4-Ch High-Performance CMOS Analog Multiplexers
FEATURES
Low on-resistance - RDS(on): 100 Ω
Low charge injection - Q: 20 pC
Fast transition time - tTRANS: 160 ns
Low power - ISUPPLY: 10 A
Single supply capability
44 V supply max. rating
TTL compatible logic
Compliant to RoHS directive 2002/95/EC
BENEFITS
Reduced switching errors
Reduced glitching
Improved data throughput
Reduced power consumption
Increased ruggedness
Wide supply ranges (± 5 V to ± 20 V)
APPLICATIONS
Data acquisition systems
Audio signal routing
ATE systems
Battery powered systems
High rel systems
Single supply systems
Medical instrumentation
DESCRIPTION
The DG408 is an 8 channel single-ended analog multiplexer
designed to connect one of eight inputs to a common output
as determined by a 3-bit binary address (A0, A1, A2). The
DG409 is a dual 4 channel differential analog multiplexer
designed to connect one of four differential inputs to a
common dual output as determined by its 2-bit binary
address (A0, A1). Break-before-make switching action
protects against momentary crosstalk between adjacent
channels.
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up
to the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (Ax)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
Applications for the DG408, DG409 include high speed data
acquisition, audio signal switching and routing, ATE
systems, and avionics. High performance and low power
dissipation make them ideal for battery operated and remote
instrumentation applications.
Designed in the 44 V silicon-gate CMOS process, the
absolute maximum voltage rating is extended to 44 V.
Additionally, single supply operation is also allowed. An
epitaxial layer prevents latchup.
For additional information please see Technical Article
TA201.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
* Pb containing terminations are not RoHS compliant, exemptions may apply
S3
A0
S6
D
S4
A1
S8
S7
EN
Dual-In-Line,
SOIC and TSSOP
A2
V-
GND
S1
V+
S2
S5
Decoders/Drivers
1
2
3
4
5
6
7
16
15
14
13
12
11
10
Top View
89
DG408
Dual-In-Line,
SOIC and TSSOP
9
A0
Da
A1
Db
EN
GND
V-
V+
S1a
S1b
S2a
S2b
S3a
S3b
S4a
S4b
Decoders/Drivers
1
2
3
4
5
6
7
16
15
14
13
12
11
10
Top View
8
DG409