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參數(shù)資料
| 型號(hào)： | 5962-9204003HXX |
| 元件分類(lèi)： | 電源模塊 |
| 英文描述： | 2-OUTPUT 15 W DC-DC REG PWR SUPPLY MODULE |
| 封裝： | STANDARD PACKAGE-10 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | 5962-9204003HXX |
3
AHE2812D
TABLE I. Electrical Performance Characteristics - Continued
Test
Symbol
Conditions
-55
°C ≤ T
C
≤ +125°C
VIN = 28 V dc ±5%, CL = 0 unless
otherwise specified
Group A
Subgroups
Device
Type
Limits
Unit
Min
Max
Switching
9/
frequency
FS
IOUT = ±625 mA
4,5,6
01
225
275
KHz
02
225
245
03
250
275
Output response to step transient
load changes
7/
VOTLOAD
50 percent load to/from 100 percent load
4
All
-300
+300
mV pk
5,6
-450
+450
No load to/from 50 percent load
4
All
-500
+500
5,6
-750
+750
Recovery time step transient load
changes
1/ 7/
TTLOAD
50 percent load to/from 100 percent load
4
All
70
s
5,6
100
No load to 50 percent load
4,5,6
All
1500
50 percent load to no load
4,5,6
All
5
ms
Output response to transient step
line changes
5/ 12/
VOTLINE
Input step 17 TO 40 V dc
4,5,6
All
1200
mV pk
Input step 40 TO 17 V dc
4,5,6
All
-1500
Recovery time transient step
line changes
1/ 5/ 12/
TTLINE
Input step 17 TO 40 V dc
4,5,6
All
4
ms
Input step 40 TO 17 V dc
4,5,6
All
4
Turn on overshoot
9/
VTonOS
IOUT = 0 and ±625 mA
4,5,6
All
600
mV pk
Turn on delay
2/ 9/
TonD
IOUT = 0 and ±625 mA
4,5,6
All
10
ms
Load fault recovery
12/
TrLF
4,5,6
All
10
ms
Notes:
1/ Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1 percent of VOUT at 50 percent load.
2/ Turn on delay time measurement is for either a step application of power at the input or the removal of a ground signal from the inhibit pin (pin 2) while power is applied to the
input.
3/ An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit protection and is the condition of maximum
power dissipation.
4/ Total power at both outputs. For operation at 16 V dc input, derate output power by 33 percent.
5/ Input step transition time between 2 and 10 microseconds.
6/ Capacitive load may be any value from 0 to the maximum limit without compromising dc performance. A capacitive load in excess of the maximum limit will not
disturb loop stability but may interfere with the operation of the load fault detection circuitry, appearing as a short circuit during turn on.
7/ Load step transition time between 2 and 10 microseconds.
8/ Bandwidth guaranteed by design. Tested for 20 KHz to 2 MHz.
9/ Tested at each output.
10/ When operating with unbalanced loads, at least 25 percent of the load must be on the positive output to maintain regulation.
11/ Parameter guaranteed by line and load regulation tests.
12/ Parameter shall be tested as part of design characterization and after design or process changes. Thereafter parameters shall be guaranteed to the limits specified in Table I.
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