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參數(shù)資料
| 型號： | 5962-9169101M3X |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 封裝： | LCC-28 |
| 文件頁數(shù)： | 26/48頁 |
| 文件大?。?/td> | 647K |
| 代理商： | 5962-9169101M3X |
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Power Supply Connections
VD+ - Positive Digital Power, PIN 7.
Positive digital power supply. Nominally +5 volts.
VD- - Negative Digital Power, PIN 1.
Negative digital power supply. Nominally -5 volts.
DGND - Digital Ground, PIN 6.
Digital ground [reference].
VA+ - Positive Analog Power, PIN 25.
Positive analog power supply. Nominally +5 volts.
VA- - Negative Analog Power, PIN 23.
Negative analog power supply. Nominally -5 volts.
AGND - Analog Ground, PIN 22.
Analog ground reference.
Oscillator
CLKIN - Clock Input, PIN 3.
All conversions and calibrations are timed from a master clock which can be externally
supplied by driving CLKIN [this input TTL-compatible, CMOS recommended].
XOUT - Crystal Output, PIN 4.
The master clock can be generated by tying a crystal across the CLKIN and XOUT pins. If an
external clock is used, XOUT must be left floating.
Digital Inputs
HOLD - Hold, PIN 12.
A falling transition on this pin sets the CS5101A or CS5102A to the hold state and initiates a
conversion. This input must remain low for at least 1/tclk + 20 ns. When operating in Free Run
Mode, HOLD is disabled, and should be tied to DGND or VD+.
CRS/FIN - Coarse Charge/Fine Charge Control, PIN 10.
When brought high during acquisition time, CRS/FIN forces the CS5101A or CS5102A into
coarse charge state. This engages the internal buffer amplifier to track the analog input and
charges the capacitor array much faster, thereby allowing the CS5101A or CS5102A to track
high slewing signals. In order to get an accurate sample, the last coarse charge period before
initiating a conversion (bringing HOLD low) must be longer than 0.75
s (CS5101A) or
3.75
s (CS5102A). Similarly, the fine charge period immediately prior to conversion must be
at least 1.125
s (CS5101A) or 5.625 s (CS5102A). The CRS/FIN pin must be low during
conversion time. For normal operation, CRS/FIN should be tied low, in which case the
CS5101A or CS5102A will automatically enter coarse charge for 6 clock cycles immediately
after the end of conversion.
CS5101A CS5102A
32
DS45F2
相關(guān)PDF資料 |
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| 5962-9169102MXA | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
| 5962-9169201M3A | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 5962-9169202M3A | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 5962-9169201M3X | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 5962-9169201MXX | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
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