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參數(shù)資料
| 型號(hào)： | 5962-8980301XA |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 模擬運(yùn)算功能 |
| 英文描述： | LOG OR ANTILOG AMPLIFIER, 90 MHz BAND WIDTH, MBCY8 |
| 封裝： | CM-8 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 356K |
| 代理商： | 5962-8980301XA |
SL523
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following condltions (unless otherwise stated)
Ambient temperature = 22
°C ± 2°C; Source impedance = 10; Supply voltage = +6V; Load impedance = 8pF;
Frequency = 60MHz; DC connection between Pin 6 and 7
Min.
Typ.
Max.
Small signal voltage gain
B
22.6
24
25.4
dB
C
22
24
26
dB
Small signal voltage gain
B
22
24
26
dB
C
21.4
24
26.6
dB
Gain variation (set of 8)
0.5
0.75
dB
Frequency = 60MHz
Upper cut-off frequency
B, C
120
150
MHz
Lower cut-off frequency
B, C
10
15
MHz
Propagation delay
B, C
4
ns
Maximum rectified video
B
1.9
2.1
2.3
mA
output current
C
1.8
2.1
2.4
mA
Maximum input signal before
B, C
1.8
1.9
V RMS
See note below
overload
Noise figure
4
5.25
dB
Source impedance 450
Supply current
B
25
30
36
mA
C
23
30
38
mA
Maximum RF output voltage
B, C
1.2
V p-p
Value
Units
Conditions
Circuits
Characteristic
Frequency = 30MHz
Frequency = 60MHz
Fig.4 Voltage gain v. frequency (typical)
OPERATING NOTES
The amplifier is designed to be directly coupled (seeFig.5)
The fourth stage in an untuned cascade will give full output
on the broad band noise generated by the first stage.
Noise may be reduced by inserting a single tuned circuit in
the chain As there is a large mismatch between stages a
simple shunt or series circuit cannot be used The network
chosen must give unity voltage gain at resonance to avoid
distorting the log law The typical value for input impedance is
500
in parallel with 5pF and the output impedance is typically
30
.
Although a 1nF supply line decoupling capacitor is
included in the can an extra capacitor is required when the
amplifiers are cascaded Minimum values for this capacitor
are: 2 stages - 3nF, 3 or more stages 30nF
In cascades of 3 or more stages care must be taken to
avoid oscillations caused either by inductance common to the
input and output earths of the strip or by feedback along the
common video line The use of a continuous earth plane will
avoid earth inductance problems and a common base
amplifier in the video line isolating the first two stages as
shown in Fig 6 will eliminate feedback on the video line
Fig.3 Rectified output current v. input signal (typical)
Note:- Overload occurs when the input signal reaches a level sufficient to forward bias the base-collector junction to the input
transistor on peaks
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