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參數(shù)資料
| 型號(hào)： | 5962-8961604VX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP18 |
| 封裝： | DIP-18 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 384K |
| 代理商： | 5962-8961604VX |
Detailed Description
The MAX5422/MAX5423/MAX5424 contain a resistor
array with 255 resistive elements. The MAX5422 has a
total end-to-end resistance of 50k
Ω; the MAX5423 has
an end-to-end resistance of 100k
Ω; and the MAX5424
has an end-to-end resistance of 200k
Ω. The
MAX5422/MAX5423/MAX5424 allow access to the high,
low, and wiper terminals for a standard voltage-divider
configuration. H, L, and W can be connected in any
desired configuration as long as their voltages fall
between GND and VDD.
A simple, 3-wire, SPI serial interface moves the wiper
among the 256 tap points. The nonvolatile memory
stores the wiper position and recalls the stored wiper
position upon power-up. The nonvolatile memory is
guaranteed for 50 years for wiper data retention and up
to 200,000 wiper store cycles.
Analog Circuitry
The MAX5422/MAX5423/MAX5424 consist of a resistor
array with 255 resistive elements; 256 tap points are
accessible to the wiper, W, along the resistor string
between H and L. Select the wiper tap point by pro-
gramming the potentiometer through the 3-wire (SPI)
interface. Eight data bits, and a control byte program
the wiper position. The H and L terminals of the
MAX5422/MAX5423/MAX5424 are similar to the two
end terminals of a mechanical potentiometer. The
MAX5422/MAX5423/MAX5424 feature power-on reset
circuitry that loads the wiper position from the non-
volatile memory at power-up.
Digital Interface
The MAX5422/MAX5423/MAX5424 use a 3-wire, SPI-
compatible, serial data interface (Figure 1 and 2). This
write-only interface contains three inputs: chip-select
MAX5422/MAX5423/MAX5424
256-Tap, Nonvolatile, SPI-Interface,
Digital Potentiometers
_______________________________________________________________________________________
7
PIN
NAME
FUNCTION
1VDD
Power-Supply Input. Bypass VDD with a 0.1F capacitor from VDD to GND.
2
SCLK
Serial-Interface Clock Input
3
DIN
Serial-Interface Data Input
4
CS
Active-Low Digital-Input Chip Select
5
GND
Ground
6L
Low Terminal. The voltage at L can be greater than or less than the voltage at H. Current can flow into or
out of L.
7
W
Wiper Terminal
8H
High Terminal. The voltage at H can be greater than or less than the voltage at L. Current can flow into or
out of H.
—
EP
Exposed Pad. The exposed pad is not internally connected. Connect to GND or leave floating.
Pin Description
SCLK
CS
DIN
tCS0
tDS
tCL
tCH
tDH
tCP
tCSH
tCS1
tCSW
tCSS
Figure 1. Digital Interface and Timing Diagram
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