參數(shù)資料
型號: 5962-8961603VX
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP18
封裝: DIP-18
文件頁數(shù): 3/14頁
文件大?。?/td> 291K
代理商: 5962-8961603VX
MAX5417/MAX5418/MAX5419
256-Tap, Nonvolatile, I2C-Interface,
Digital Potentiometers
______________________________________________________________________________________
11
Message Format for Writing
A write to the MAX5417/MAX5418/MAX5419 consists of
the transmission of the device’s slave address with the
8th bit set to zero, followed by at least 1 byte of infor-
mation (Figure 7). The 1st byte of information is the
command byte. The bytes received after the command
byte are the data bytes. The 1st data byte goes into the
internal register of the MAX5417/MAX5418/MAX5419 as
selected by the command byte (Figure 8).
Command Byte
Use the command byte to select the source and desti-
nation of the wiper data (nonvolatile or volatile memory
registers) and swap data between nonvolatile and
volatile memory registers (see Table 2).
Command Descriptions
VREG: The data byte writes to the volatile memory reg-
ister and the wiper position updates with the data in the
volatile memory register.
NVREG: The data byte writes to the nonvolatile memo-
ry register. The wiper position is unchanged.
NVREGxVREG: Data transfers from the nonvolatile
memory register to the volatile memory register (wiper
position updates).
VREGxNVREG: Data transfers from the volatile memo-
ry register into the nonvolatile memory register.
A
0
SLAVE ADDRESS
CONTROL BYTE
DATA BYTE
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
NOP/W
1 BYTE
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
D15
D14 D13 D12 D11 D10
D9
D8
D1
D0
D3
D2
D5
D4
D7
D6
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX5417/MAX5418/MAX5419 REGISTERS
S
A
P
S
A
0
SLAVE ADDRESS
CONTROL BYTE
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
NOP/W
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
D15
D14
D13
D12
D11
D10
D9
D8
CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION
AP
Figure 7. Command Byte Received
Figure 8. Command and Single Data Byte Received
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