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參數(shù)資料
| 型號： | 5962-8876404XX |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | 0.600 INCH, GLASS SEALED, CERDIP-28 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 366K |
| 代理商： | 5962-8876404XX |
AD7824/AD7828
REV. D
–3–
TIMING CHARACTERISTICS1 (V
DD = 5 V; VREF(+) = 5 V; VREF(–) = GND = 0 V unless otherwise noted)
Limit at
Limit at 25 CTMIN, TMAX
TMIN, TMAX
Parameter
(All Grades)
(K, L, B, C Grades)
(T, U Grades)
Unit
Conditions/Comments
tCSS
0
ns min
CS to RD Setup Time
tCSH
0
ns min
CS to RD Hold Time
tAS
0
ns min
Multiplexer Address Setup Time
tAH
30
35
40
ns min
Multiplexer Address Hold Time
tRDY
2
40
60
ns max
CS to RDY Delay. Pull-Up
Resistor 5 k
.
tCRD
2.0
2.4
2.8
s max
Conversion Time, Mode 0
tACC1
3
85
110
120
ns max
Data Access Time after
RD
tACC2
3
50
60
70
ns max
Data Access Time after
INT, Mode 0
tlNTH
2
40
65
70
ns typ
RD to INT Delay
75
100
ns max
tDH
4
60
70
ns max
Data Hold Time
tP
500
600
ns min
Delay Time between Conversions
tRD
60
80
ns min
Read Pulsewidth, Mode 1
600
500
400
ns max
NOTES
1Sample tested at 25
°C to ensure compliance. All input control signals are specified with tr = tf = 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2C
L = 50 pF.
3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
Figure 1. Load Circuits for Data Access Time Test
Figure 2. Load Circuits for Data Hold Time Test
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