參數(shù)資料
型號(hào)： 5962-87802012A
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, CQCC20
封裝： CERAMIC, LCC-20
文件頁(yè)數(shù)： 6/21頁(yè)
文件大小： 440K
代理商： 5962-87802012A
TLC7226C, TLC7226I, TLC7226M
QUADRUPLE 8BIT DIGITALTOANALOG CONVERTERS
SLAS060F JANUARY 1995 REVISED APRIL 2009
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
staircase window comparator (continued)
REF
OUTB
OUTA
OUTD
OUTC
AGND
Window 1
Window 2
Window 3
Windows 1 and 2
Windows 2 and 3
Figure 13. Overlapping Window Structure
output buffer amplifier
The unity-gain output amplifier is capable of sourcing 5 mA into a 2-k
load and can drive a 3300-pF capacitor.
The output can be shorted to AGND indefinitely or it can be shorted to any voltage between VSS and VDD
consistent with the maximum device power dissipation.
multiplying DAC
The TLC7226 can be used as a multiplying DAC when the reference signal is maintained between 2 V and
VDD 4 V. When this configuration is used, VDD should be 14.25 V to 15.75 V. A low output-impedance buffer
should be used so that the input signal is not loaded by the resistor ladder. Figure 14 shows the general
schematic.
_
+
_
+
DAC
AGND
DGND
56
1/4 TLC7226
4
15 V
Vref
OP07
15 V
R1
R2
AC Reference
Input Signal
VO
Figure 14. AC Signal Input Scheme
相關(guān)PDF資料
PDF描述
5962-87802012C PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, CQCC20
TLC7226CDW PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, PDSO20
TLC7226IDW PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, PDSO20
TLC7226IDWR PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, PDSO20
TLC7226MFKB PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 8-BIT DAC, CQCC20
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