參數(shù)資料
型號： 5962-87700012A
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CQCC20
封裝： CERAMIC, LLCC-20
文件頁數(shù)： 7/12頁
文件大?。?/td> 256K
代理商： 5962-87700012A
AD7524M
Advanced LinCMOS 8BIT MULTIPLYING
DIGITALTOANALOG CONVERTER
SGLS028A SEPTEMBER 1989 REVISED MARCH 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
electrical characteristics over recommended operating free-air temperature range, Vref = 10 V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 5 V
VDD = 15 V
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
IIH
High-level input current
VI = VDD
Full-range
10
A
IIH
High-level input current
VI = VDD
25
°C
1
A
IIL
Low-level input current
VI = 0
Full-range
10
A
IIL
Low-level input current
VI = 0
25
°C
1
A
OUT1
DB0DB7 at 0,
WR and CS at 0 V
Full-range
±400
±200
Ipkg
Output leakage
OUT1
Vref = ±10 V
25
°C
±50
nA
Ipkg
Output leakage
current
OUT2
DB0DB7 at VDD,
WR and CS at 0
Full-range
±400
±200
nA
OUT2
Vref = ±10 V
25
°C
±50
Quiescent
DB0DB7 at VIHmin or VILmax
2
mA
IDD
Supply current
Standby
DB0DB7 at 0 V or VDD
Full-range
500
A
IDD
Supply current
Standby
DB0DB7 at 0 V or VDD
25
°C
100
A
kSVS
Supply voltage sensitivity,
VDD = 10%
Full-range
0.16
0.04
%/%
kSVS
Supply voltage sensitivity,
gain/VDD
VDD = 10%
25
°C
0.002
0.02
0.001
0.02
pF
Ci
Input capacitance, DB0DB7,
WR, CS
VI = 0
5
pF
OUT1
DB0DB7 at 0, WR and CS at 0 V
30
Co
Output
OUT2
DB0DB7 at 0, WR and CS at 0 V
120
pF
Co
Output
capacitance
OUT1
DB0DB7 at VDD, WR and CS at 0 V
120
pF
capacitance
OUT2
DB0DB7 at VDD, WR and CS at 0 V
30
Reference input impedance
(REF to GND)
5
20
5
20
k
operating characteristics over recommended operating free-air temperature range, Vref = 10 V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 5 V
VDD = 15 V
UNIT
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNIT
Linearity error
±0.2
±0.2 %FSR
Gain error
See Note 1
Full range
±1.4
±0.6
%FSR
Gain error
See Note 1
25
°C
±1
±0.5
%FSR
Settling time (to 1/2 LSB)
See Note 2
100
ns
Propagation delay from digital input to
90% of final analog output current
See Note 2
80
ns
Feedthrough at OUT1 or OUT2
Vref = ± 10 V (100 kHz sinewave),
Full range
0.5
%FSR
Feedthrough at OUT1 or OUT2
Vref = ± 10 V (100 kHz sinewave),
WR and CS at 0,
DB0DB7 at 0
25
°C
0.25
%FSR
Temperature coefficient of gain
TA = 25°C to tmin or tmax
±0.004
±0.001
%FSR/
°C
NOTES:
1. Gain error is measured using the internal feedback resistor. Nominal Full Scale Range (FSR) = Vref 1 LSB.
2. OUT1 load = 100
, Cext = 13 pF, WR at 0 V, CS at 0 V, DB0DB7 at 0 V to VDD or VDD to 0 V.
相關PDF資料
PDF描述
5962-8770001EA PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP16
5962-8770002EX PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP16
5962-8770003EX PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP16
5962-8770101RX DUAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP20
5962-8770102RX DUAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP20
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