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參數(shù)資料
| 型號(hào)： | 5962-8670402VPA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1 A SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, CDIP8 |
| 封裝： | CERAMIC, DIP-8 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 295K |
| 代理商： | 5962-8670402VPA |
80
60
40
20
0
-45
-90
-135
-180
V
olta
g
e
Gain
-
dB
Phase
Mar
gin
-
°
Av
θ
10
100
1 k
10 k
100 k
1 M
10 M
f - Frequenc y - Hz
4.7 kW
1 kW
ERROR AMP
ADJUST
4.7 kW
5 kW
ISENSE
ADJUST
2N2222
100 kW
R1
1
2
3
4
8
7
6
5
COMP
VFB
ISENSE
RT / CT
CT
0.1 mF
A
1 kW 1 W
VREF
VCC
OUTPUT
GROUND
VREF
VCC
OUTPUT
GROUND
8
3
1 kW
330 W
SHUTDOWN
500 W
To Current
SENSE RESISTOR
VREF
ISENSE
1
SHUTDOWN
COMP
SLUS981 – MARCH 2010
www.ti.com
ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE
OPEN-LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypas
capacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer are
used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
SHUTDOWN TECHNIQUES
Shutdown of the UC1843 can be accomplished by two methods; either raise pin 3 above 1 V or pull pin 1 below
a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock
cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown
may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At
this pint the reference turns off, allowing the SCR to reset.
8
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): UC1843-SP
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