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參數(shù)資料
| 型號： | 5962-0520601QZC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 6/42頁 |
| 文件大小： | 1310K |
| 代理商： | 5962-0520601QZC |
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Typical Electrical Characteristics (Continued)
AC Parameters
The following specifications apply after calibration for V
A = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mV
P-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating,
Non-Extended Control Mode, SDR Mode, R
EXT = 3300 ±0.1%, Analog Signal Source Impedance = 100Ω Differential. (Notes 5,
Symbol
Parameters
Conditions
Notes
Typical
(Note 7)
Units
f
CLK1
Maximum Input Clock Frequency
DES Mode
1.0
GHz
f
CLK2
Minimum Input Clock Frequency
Normal Mode (non DES)
200
MHz
f
CLK2
Minimum Input Clock Frequency
DES Mode
500
MHz
Input Clock Duty Cycle
200 MHz
≤ Input clock frequency
≤ 1 GHz (Normal Mode)
50
% (min)
% (max)
Input Clock Duty Cycle
500 MHz
≤ Input clock frequency
≤ 1 GHz (DES Mode)
50
% (min)
% (max)
t
CL
Input Clock Low Time
500
ps (min)
t
CH
Input Clock High Time
500
ps (min)
DCLK Duty Cycle
50
% (min)
% (max)
t
RS
Reset Setup Time
150
ps
t
RH
Reset Hold Time
250
ps
t
SD
Syncronizing Edge to DCLK Output
Delay
f
CLKIN = 1.0 GHz
3.53
ns
f
CLKIN = 200 MHz
3.85
ns
t
LHT
Differential Low to High Transition
Time
10% to 90%, C
L = 2.5 pF
250
ps
t
HLT
Differential High to Low Transition
Time
10% to 90%, C
L = 2.5 pF
250
ps
t
OSK
DCLK to Data Output Skew
50% of DCLK transition to 50% of Data
transition, SDR Mode
and DDR Mode, 0° DCLK
±50
ps (max)
t
SU
Data to DCLK Set-Up Time
DDR Mode, 90° DCLK
1
ns
t
H
DCLK to Data Hold Time
DDR Mode, 90° DCLK
1
ns
t
AD
Sampling (Aperture) Delay
Input CLK+ Fall to Acquisition of Data
1.3
ns
t
AJ
Aperture Jitter
0.4
ps rms
t
OD
Input Clock to Data Output Delay (in
addition to Pipeline Delay)
50% of Input Clock transition to 50% of
Data transition
3.1
ns
Pipeline Delay (Latency)
DI Outputs
(Notes 10,
13
Input Clock
Cycles
DId Outputs
14
DQ Outputs Normal Mode
13
DQ Outputs DES Mode
13.5
DQd Outputs Normal Mode
14
DQd Outputs Normal Mode
14.5
Over Range Recovery Time
Differential V
IN step from ±1.2V to 0V to
get accurate conversion
1
Input Clock
Cycle
t
WU
PD low to Rated Accuracy Conversion
(Wake-Up Time)
500
ns
f
SCLK
Serial Clock Frequency
100
MHz
t
SSU
Data to Serial Clock Setup Time
2.5
ns (min)
t
SH
Data to Serial Clock Hold Time
1
ns (min)
t
CAL
Calibration Cycle Time
7.1x105
Clock Cycles
www.national.com
14
ADC08D1000QML
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| 5962-0520601VZX | PROPRIETARY METHOD ADC, CQFP128 |
| 5962-0520601VZC | PROPRIETARY METHOD ADC, CQFP128 |
| 5962-0520601VZX | PROPRIETARY METHOD ADC, CQFP128 |
| 5962-0520601VZC | PROPRIETARY METHOD ADC, CQFP128 |
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