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參數(shù)資料
| 型號(hào)： | 57C51C-35 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HIGH SPEED 16K x 8 CMOS PROM/RPROM |
| 中文描述： | 高速16K的× 8的CMOS胎膜早破/ RPROM |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 53K |
| 代理商： | 57C51C-35 |
WS57C51C
2-50
SYMBOL
PARAMETER
CONDITIONS
TYP
(5)
MAX
UNITS
C
IN
Input Capacitance
V
IN
= 0V
4
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
C
VPP
V
PP
Capacitance
V
PP
= 0 V
18
25
pF
CAPACITANCE
(4)
T
A
= 25°C, f = 1 MHz
30 pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
98
2.01 V
D.U.T.
A.C. TESTING INPUT/OUTPUT WAVEFORM
TEST LOAD
(High Impedance Test Systems)
3.0
0.0
1.5
1.5
TEST
POINTS
NOTE:
6. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters.
A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between V
CC
and ground is recommended.
Inadequate decoupling may result in access time degradation or other transient performance failures.
NOTES:
4. This parameter is only sampled and is not 100% tested.
5.Typical values are for T
A
= 25°C and nominal supply voltages.
A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V
for a logic "0." Timing measurements are made at 1.5 V for
input and output transitions in both directions.
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