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參數(shù)資料
| 型號(hào)： | 575R15ID12M0000 |
| 廠(chǎng)商： | CTS CORP |
| 元件分類(lèi)： | TCVCXO, sine |
| 英文描述： | TCVCXO, CLIPPED SINE OUTPUT, 12 MHz |
| 封裝： | GREEN, HERMETIC SEALED, CERAMIC PACKAGE-4 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | 575R15ID12M0000 |
Document No. 008-0307-0
Page 3 - 4
Rev. E
Model 575
TCXO/VC-TCXO – Clipped Sine Wave
MECHANICAL SPECIFICATIONS
SUGGESTED SOLDER PAD GEOMETRY
.225 [5.71]
.071 [1.80]
.047 [1.20]
1
BYPASS
C
4
.165 [4.20]
2
[mm]
Key:
3
Inch
CBYPASS should be ≥ 0.01 uF.
MARKING INFORMATION
1. M575 - CTS Model Series.
2. ● – Pin 1 identifier.
3. C – CTS identifier.
4. D – Date code. See Table II for codes.
5. XXX – Frequency code. See Table I for codes.
Complete CTS part number, frequency value and
date code information must appear on reel and
carton labels.
PACKAGE DRAWING
TYP
(0.2)
0.008
{Pads 1 - 4}
(0.3 ±0.1)
(2.0)
MAX
(5.08 ±0.2)
0.200 ±0.004
0.276 ±0.008
0.079
(5.0 ±0.2)
0.197 ±0.008
0.157 ±0.004
(4.0 ±0.1)
Key: (mm)
Inch
2
3
4
0.031 ±0.004
(0.8 ±0.1)
1
0.012 ±0.004
(7.0 ±0.2)
0.055 ±0.004
(1.4 ±0.1)
NOTES
1. DO NOT make connections to non-labeled pins.
Castellation pins may have internal connections
used in the manufacturing process.
2. Termination pads (e4); barrier plating is nickel
(Ni) with gold (Au) flash plate.
3. Reflow conditions per JEDEC J-STD-020,
260°C maximum.
M575
● CDXXX
TABLE I – FREQUENCY CODING
FREQUENCY
MARKING
CODE
FREQUENCY
MARKING
CODE
FREQUENCY
MARKING
CODE
FREQUENCY
MARKING
CODE
10.000 MHz
100
15.360 MHz
153
18.432 MHz
184
25.000 MHz
250
10.240 MHz
102
16.000 MHz
160
19.200 MHz
192
26.000 MHz
260
12.000 MHz
120
16.367 MHz
16A
19.440 MHz
194
27.000 MHz
270
12.288 MHz
122
16.367667 MHz
16B
19.680 MHz
196
32.000 MHz
320
12.800 MHz
128
16.368 MHz
16C
19.800 MHz
198
32.512 MHz
325
13.000 MHz
130
16.369 MHZ
16D
19.998 MHz
199
32.768 MHz
327
13.500 MHz
135
16.384 MHz
163
20.000 MHz
200
38.880 MHz
388
14.000 MHz
140
16.800 MHz
168
20.480 MHz
204
40.000 MHz
400
14.400 MHz
144
18.000 MHz
180
24.000 MHz
240
Not all frequencies listed may be available for this design.
TABLE II – DATE CODE
2001
2005
2009
2013
2017
A
B
C
D
E
F
G
H
J
K
L
M
2002
2006
2010
2014
2018
N
P
Q
R
S
T
U
V
W
X
Y
Z
2003
2007
2011
2015
2019
a
b
c
d
e
f
g
h
j
k
l
m
2004
2008
2012
2016
2020
n
p
q
r
s
t
u
v
w
x
y
z
MONTH
JAN
FEB
MAR
DEC
YEAR
AUG
SEP
OCT
NOV
APR
MAY
JUN
JUL
TEST CIRCUIT – RL//CL LOAD
SUPPLY
POWER
-
+
-
+
VM
-
+
mA
Control Voltage - VC-TCXO
GND - TCXO
D.U.T.
1
0.01uF
4
2
3
Including probe
capacitance.
Ω
10K
10pF
D.U.T. PIN ASSIGNMENTS
PIN
SYMBOL
DESCRIPTION
Control Voltage – VCTCXO (Note 1)
1
VC
GND - TCXO
2
GND
Circuit & Package Ground
3
Output
Clipped Sine Wave Output
4
VCC
Supply Voltage
NOTES
1. Connect to ground for TCXO (no AFC) option.
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