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參數(shù)資料
| 型號： | 571KHAFREQDGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 10 MHz - 945 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-8 |
| 文件頁數(shù)： | 18/26頁 |
| 文件大?。?/td> | 315K |
| 代理商： | 571KHAFREQDGR |
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Si570/Si571
Rev. 0.31
25
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated " Description" on page 1.
Updated "1. Detailed Block Diagrams" on page 4 for
both XO and VCXO.
Updated the Nominal Control Voltage in Table 2, “VC
Updated tables to reflect slight performance
differences between Si570 and Si571.
Added detail to the "3.2. Frequency Programming
12.
Procedure now requires use of two frequency
configuration register sets.
Procedure now recommends disabling output at
powerup to protect equipment not expecting the
default output frequency.
Added second frequency configuration register set
to the register tables.
Added frequency configuration select register.
Updated "7. Ordering Information" on page 21 to be
consistent with the Si55x series devices.
Revision 0.2 to Revision 0.3
Updated Table 1, “Recommended Operating
Device maintains stable operation over –40 to +85 C
operating temperature range.
Supply current specifications updated.
Updated Table 4, “CLK± Output Levels and
Updated LVDS differential peak-peak swing
specifications.
Revised period jitter specifications.
page 10 to reflect the soldering temperature time at
260 C is 20–40 sec per JEDEC J-STD-020C.
Updated device programming procedure in Section
Updated "7. Ordering Information" on page 21.
Changed ordering instructions to revision D.
Revision 0.3 to Revision 0.31
12.
Corrected Step 6 to read “bit 4”.
Corrected Freeze DCO bit location in Register 137 to
bit 4 on pages 14 and 18.
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