參數(shù)資料
    型號: 571JKAFREQDGR
    廠商: SILICON LABORATORIES
    元件分類: XO, clock
    英文描述: VCXO, CLOCK, 10 MHz - 160 MHz, CMOS OUTPUT
    封裝: ROHS COMPLIANT PACKAGE-8
    文件頁數(shù): 1/26頁
    文件大?。?/td> 315K
    代理商: 571JKAFREQDGR
    Rev. 0.31 8/07
    Copyright 2007 by Silicon Laboratories
    Si570/Si571
    This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
    Si570/Si571
    PRELIMINARY DATA SHEET
    ANY-RATE I2C PROGRAMMABLE XO/VCXO
    Features
    Applications
    Description
    The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
    circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are
    user-programmable to any output frequency from 10 to 945 MHz and select
    frequencies to 1400 MHz with <1 ppb resolution. The device is programmed
    via an I2C serial interface. Unlike traditional XO/VCXOs where a different
    crystal is required for each output frequency, the Si57x uses one fixed-
    frequency crystal and a DSPLL clock synthesis IC to provide any-rate
    frequency operation. This IC-based approach allows the crystal resonator to
    provide exceptional frequency stability and reliability. In addition, DSPLL
    clock synthesis provides superior supply noise rejection, simplifying the task
    of generating low-jitter clocks in noisy environments typically found in
    communication systems.
    Functional Block Diagram
    Any-rate programmable output
    frequencies from 10 to 945 MHz and
    select frequencies to 1.4 GHz
    I2C serial interface
    3rd generation DSPLL with superior
    jitter performance
    3x better frequency stability than
    SAW-based oscillators
    Internal fixed crystal frequency
    ensures high reliability and low
    aging
    Available LVPECL, CMOS,
    LVDS, and CML outputs
    Industry-standard 5x7 mm
    package
    Pb-free/RoHS-compliant
    1.8, 2.5, or 3.3 V supply
    SONET / SDH
    xDSL
    10 GbE LAN / WAN
    Low-jitter clock generation
    Optical modules
    Clock and data recovery
    Fixed
    Frequency
    XO
    Any-rate
    10-1400 MHz
    DSPLL
    Clock
    Synthesis
    CLK-
    CLK+
    SCL
    GND
    OE
    VDD
    SDA
    VC
    ADC
    Si571 only
    Ordering Information:
    Pin Assignments:
    (Top View)
    Si5602
    Si570
    Si571
    1
    2
    3
    6
    5
    4
    NC
    GND
    OE
    VDD
    CLK+
    CLK–
    SDA
    SCL
    8
    7
    1
    2
    3
    6
    5
    4
    VC
    GND
    OE
    VDD
    CLK+
    CLK–
    SDA
    SCL
    8
    7
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