參數(shù)資料
型號: 571DJAFREQDGR
廠商: SILICON LABORATORIES
元件分類: VCXO, clock
英文描述: VCXO, CLOCK, 10 MHz - 945 MHz, CMOS OUTPUT
封裝: ROHS COMPLIANT PACKAGE-8
文件頁數(shù): 17/26頁
文件大?。?/td> 315K
代理商: 571DJAFREQDGR
Si570/Si571
24
Rev. 0.31
10. 8-Pin PCB Land Pattern
Figure 7 illustrates the 8-pin PCB land pattern for the Si570/Si571. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 7. Si570/Si571 PCB Land Pattern
Table 17. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
5.08 REF
D3
5.705 REF
e
2.54 BSC
E2
4.20 REF
GD
0.84
GE
2.00
VD
8.20 REF
VE
7.30 REF
X1
1.70 TYP
X2
1.545 TYP
Y1
2.15 REF
Y2
1.3 REF
ZD
6.78
ZE
6.30
Note:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition
(MMC).
4. Controlling dimension is in millimeters (mm).
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