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參數(shù)資料
| 型號： | 571DJAFREQDG |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 10 MHz - 945 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-8 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 315K |
| 代理商： | 571DJAFREQDG |
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Si570/Si571
Rev. 0.31
13
3.3. I2C Interface
The control interface to the Si570 is an I2C-compatible
2-wire bus for bidirectional communication. The bus
consists of a bidirectional serial data line (SDA) and a
serial clock input (SCL). Both lines must be connected
to the positive supply via an external pullup. Fast mode
operation is supported for transfer rates up to 400 kbps
as specified in the I2C-Bus Specification standard.
Figure 3 shows the command format for both read and
write access. Data is always sent MSB first. The timing
specifications and timing diagram for the I2C bus can be
found in the I2C-Bus Specification standard (fast mode
operation). The device I2C address is specified in the
part number.
Figure 3. I2C Command Format
AData
A
Data
P
A
1
Slave Address
S
A
Byte Address
A
0
Slave Address
S
1
From master to slave
From slave to master
A – Acknowledge (SDA LOW)
S – START condition
P – STOP condition
Write Command
Read Command
Address auto incremented after each data read or write
P
A
Data
A
Data
A
Byte Address
A
0
Slave Address
S
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