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參數(shù)資料
| 型號(hào)： | 556G-01 |
| 英文描述： | BROADCOM 25 MHZ LVDS CLOCK |
| 中文描述： | 博通25兆赫LVDS時(shí)鐘 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 113K |
| 代理商： | 556G-01 |
MDS 556-01 B
2
Revision 020204
Integrated Circuit Systems
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
Broadcom 25 MHz LVDS Clock
ICS556-01
Pin Assignment
Pin Descriptions
External Component Selection
The ICS556-01 requires a minimum number of external
components for proper operation. A 100
termination
resistor between CLK and CLK is provided on-chip.
Decoupling Capacitors
A decoupling capacitor of 0.01
μ
F should be connected
between VDD and GND on pins 2 and 3 as close to the
ICS556-01 as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100
differential transmission line environment, LVDS drivers
require a matched load termination of 100
across near
the receiver input. For a multiple LVDS outputs buffer, if
only partial outputs are used, it is recommended to
terminate the un-used outputs.
X 2
X 1
V D D
G N D
C L K
1
2
3
4
8
7
6
5
I C S 5 5 6 - 0 1
8 P i n ( 1 7 3 m i l ) T S S O P o r S O I C
C L K
G N D
O E
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1
Input
Crystal connection.
2
VDD
Power
Power supply. Connect to 2.5 V.
3
GND
Power
Connect to ground.
4
GND
Power
Connect to ground.
5
CLK
Output
Inverting differential clock output.
6
CLK
Power
Differential clock output.
7
OE
Input
Output Enable. Internal pull-up resistor.
8
X2
Input
Crystal connection.
F I G U R E 2 . T Y P I C A L L V D S
D R I V E R T E R M I N A T I O N
R1
100 ohm
+
-
2.5V
2.5V
100 Ohm Differential Transmission Line
LVDS_Driver
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