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參數資料
| 型號： | 552ARI01LF |
| 英文描述： | Oscillator, Multiplier, and Buffer with 8 Outputs |
| 中文描述： | 振蕩器，乘數，并與8個輸出緩沖區(qū) |
| 文件頁數： | 7/10頁 |
| 文件大?。?/td> | 116K |
| 代理商： | 552ARI01LF |
Oscillator, Multiplier, and Buffer with 8 Outputs
MDS 552A-01 B
7
Revision 010906
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS552A-01
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS552A-01 must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01μF must be connected
between each VDD and GND on pins 4 and 6, and 16
and 14. Other VDDs and GNDs can be connected to
these pins or directly to their respective ground planes.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-12 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 18 pF
load capacitance, two 12 pF capacitors should be
used. For a clock input, connect it X1/ICLK and leave
X2 unconnected (floating).
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01μF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33
series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 552ARI-01LF | 功能描述:時鐘發(fā)生器及支持產品 OSCILLATOR, BUFFER, AND MULTIPLIER RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 552ARI-01LFT | 功能描述:時鐘發(fā)生器及支持產品 OSCILLATOR, BUFFER, AND MULTIPLIER RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 552B110KBO1 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:7/8inch (22.2 mm) Three Turn Wirewound Upper Grade Precision Potentiometer |
| 552BA000121DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ/666.51429MHZ VCXO LVDS 6PIN - Tape and Reel |
| 552BA000260DG | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays |
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