- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄248729 > 550VAFREQBG (SILICON LABORATORIES) VCXO, CLOCK, 10 MHz - 160 MHz, CMOS OUTPUT PDF資料下載
參數(shù)資料
| 型號(hào)： | 550VAFREQBG |
| 廠商： | SILICON LABORATORIES |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | VCXO, CLOCK, 10 MHz - 160 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-6 |
| 文件頁(yè)數(shù)： | 23/45頁(yè) |
| 文件大?。?/td> | 691K |
| 代理商： | 550VAFREQBG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)
Si550
Rev. 0.5
3
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Nominal Frequency1,2,3
fO
LVDS/CML/LVPECL
10
—
945
MHz
CMOS
10
—
160
Temperature Stability1,4
f/fO
TA = –40 to +85 C
–20
–50
–100
—
+20
+50
+100
ppm
Absolute Pull Range1,4
APR
±25
—
±150
ppm
Aging
Frequency drift over
15 year life.
——
±10
ppm
Power up Time5
tOSC
——
10
ms
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by VCNOM =3/8 xVDD.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO.
Table 4. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVPECL Output Option1
VO
mid-level
VDD – 1.42
—
VDD – 1.25
V
VOD
swing (diff)
1.1
—
1.9
VPP
VSE
swing (single-ended)
0.5
—
0.93
VPP
LVDS Output Option2
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.32
0.40
0.50
VPP
CML Output Option2
VO
mid-level
—
VDD – 0.75
—
V
VOD
swing (diff)
0.70
0.95
1.20
VPP
CMOS Output Option3
VOH
IOH =32mA
0.8 x VDD
—
VDD
V
VOL
IOL =32mA
——
0.4
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
—
350
ps
CMOS with CL = 15 pF
—
1
—
ns
Symmetry (duty cycle)
SYM
LVPECL:
VDD – 1.3 V (diff)
LVDS:
1.25 V (diff)
CMOS:
VDD/2
45
—
55
%
Notes:
1. 50
to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 571BCAFREQDG | VCXO, CLOCK, 10 MHz - 945 MHz, LVDS OUTPUT |
| 5G576E-80T-FREQ | VCXO, CLOCK, 0.625 MHz - 50 MHz, HCMOS/TTL OUTPUT |
| 575L05HC24M0000 | TCVCXO, CLIPPED SINE OUTPUT, 24 MHz |
| 575S15IA14M0000 | TCVCXO, CLIPPED SINE OUTPUT, 14 MHz |
| 575T30CD12M2880 | TCVCXO, CLIPPED SINE OUTPUT, 12.288 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 550-VC6DT2 | 制造商:MTU 制造商全稱(chēng):MTU 功能描述:DIESEL ENGINE-GENERATOR SET |
| 550WD311M040DG | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays |
| 550WD311M040DGR | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Tape and Reel |
| 550-XX04 | 制造商:DIALIGHT 制造商全稱(chēng):Dialight Corporation 功能描述:5mm LED CBI Circuit Board Indicator Top View, Single |
| 550-XX05 | 制造商:DIALIGHT 制造商全稱(chēng):Dialight Corporation 功能描述:5mm LED CBI, SO BACK HOUSING |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。