參數資料
型號: 550NE125M000DGR
廠商: SILICON LABORATORIES
元件分類: VCXO, clock
英文描述: VCXO, CLOCK, 125 MHz, LVDS OUTPUT
封裝: ROHS COMPLIANT PACKAGE-6
文件頁數: 12/14頁
文件大?。?/td> 230K
代理商: 550NE125M000DGR
Si550
Rev. 0.6
7
2. Pin Descriptions
Table 10. Si550 Pin Descriptions
Pin
Name
Type
Function
1
VC
Analog Input
Control Voltage
2
OE*
Input
Output Enable (Polarity = High):
0 = clock output disabled (outputs tri-stated)
1 = clock output enabled
3
GND
Ground
Electrical and Case Ground
4
CLK+
Output
Oscillator Output
5
CLK–
(N/A for CMOS)
Output
Complementary Output
(N/C for CMOS)
6
VDD
Power
Power Supply Voltage
*Note: OE includes 17 k
pullup resistor to VDD. See Section 3. "Ordering Information" on page 8 for details on OE polarity
ordering options.
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
(Top View)
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