- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄114587 > 550ME614M400DGR (SILICON LABORATORIES) VCXO, CLOCK, 614.4 MHz, LVPECL OUTPUT PDF資料下載
參數(shù)資料
| 型號(hào)： | 550ME614M400DGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 614.4 MHz, LVPECL OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-6 |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大小： | 230K |
| 代理商： | 550ME614M400DGR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
Si550
Rev. 0.6
5
Phase Jitter (RMS)1,2,3
for FOUT of 125 to 500 MHz
φ
J
Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.37
0.33
—
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.37
0.33
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.43
0.34
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.50
0.34
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.59
0.35
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
1.00
0.39
—
Table 6. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Period Jitter*
JPER
RMS
—
2
—
ps
Peak-to-Peak
—
14
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 5. CLK± Output Phase Jitter (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 550MH040M000DGR | VCXO, CLOCK, 40 MHz, LVPECL OUTPUT |
| 550MH166M628DGR | VCXO, CLOCK, 166.628 MHz, LVPECL OUTPUT |
| 550ND125M000DGR | VCXO, CLOCK, 125 MHz, LVDS OUTPUT |
| 550CJ153M600DGR | VCXO, CLOCK, 153.6 MHz, CMOS OUTPUT |
| 550EJ100M000DG | VCXO, CLOCK, 100 MHz, LVPECL OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 550ME622M080DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ VCXO LVPECL 6SMD - Tape and Reel |
| 550ME693M483DG | 制造商:Silicon Laboratories Inc 功能描述:VCXO, 693.483000MHZ, LVPECL, 3.3V - Trays |
| 550ME693M483DGR | 制造商:Silicon Laboratories Inc 功能描述:VCXO, 693.483000MHZ, LVPECL, 3.3V - Tape and Reel |
| 550ME693M493DG | 制造商:Silicon Laboratories Inc 功能描述:VCXO, 693.49300MHZ, LVPECL, 3.3V - Trays |
| 550ME693M493DGR | 制造商:Silicon Laboratories Inc 功能描述:VCXO, 693.49300MHZ, LVPECL, 3.3V - Tape and Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。