- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄116278 > 550MB311M040DGR (SILICON LABORATORIES) VCXO, CLOCK, 311.04 MHz, LVPECL OUTPUT PDF資料下載
參數(shù)資料
| 型號： | 550MB311M040DGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 311.04 MHz, LVPECL OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-6 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 230K |
| 代理商： | 550MB311M040DGR |
Si550
Rev. 0.6
5
Phase Jitter (RMS)1,2,3
for FOUT of 125 to 500 MHz
φ
J
Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.37
0.33
—
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.37
0.33
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.43
0.34
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.50
0.34
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.59
0.35
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
1.00
0.39
—
Table 6. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Period Jitter*
JPER
RMS
—
2
—
ps
Peak-to-Peak
—
14
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 5. CLK± Output Phase Jitter (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 550MD166M629DGR | VCXO, CLOCK, 166.629 MHz, LVPECL OUTPUT |
| 550ND074M250DGR | VCXO, CLOCK, 74.25 MHz, LVDS OUTPUT |
| 550NE125M000DGR | VCXO, CLOCK, 125 MHz, LVDS OUTPUT |
| 550CM147M456DG | VCXO, CLOCK, 147.456 MHz, CMOS OUTPUT |
| 550FA311M000DGR | VCXO, CLOCK, 311 MHz, LVDS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 550MC000106DG | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 132.8125MHZ VCXO LVPECL 6SMD - Trays |
| 550MC000106DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 132.8125MHZ VCXO LVPECL 6SMD - Tape and Reel |
| 550MC000109DG | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 142.29911MHZ VCXO LVPECL 6SMD - Trays |
| 550MC000109DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 142.29911MHZ VCXO LVPECL 6SMD - Tape and Reel |
| 550MC644M530DG | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。