參數(shù)資料
型號: 550CE67M5000BGR
廠商: SILICON LABORATORIES
元件分類: VCXO, clock
英文描述: VCXO, CLOCK, 67.5 MHz, CMOS OUTPUT
封裝: ROHS COMPLIANT, SMD, 6 PIN
文件頁數(shù): 43/44頁
文件大?。?/td> 556K
代理商: 550CE67M5000BGR
Si550
8
Rev. 0.5
4. Outline Diagram and Suggested Pad Layout
Figure 2 illustrates the package details for the Si550. Table 11 lists the values for the dimensions shown in the
illustration.
Figure 2. Si550 Outline Diagram
Table 11. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
A
1.45
1.65
1.85
b1.2
1.4
1.6
c0.60 TYP.
D
7.00 BSC.
D1
6.10
6.2
6.30
e
2.54 BSC.
E
5.00 BSC.
E1
4.30
4.40
4.50
L
1.07
1.27
1.47
S
1.815 BSC.
R
0.7 REF.
aaa
0.15
bbb
0.15
ccc
0.10
ddd
0.10
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