參數(shù)資料
    型號： 550AE155M520BGR
    廠商： SILICON LABORATORIES
    元件分類： VCXO, clock
    英文描述： VCXO, CLOCK, 155.52 MHz, LVPECL OUTPUT
    封裝： ROHS COMPLIANT, SMD, 6 PIN
    文件頁數(shù)： 12/44頁
    文件大?。?/td> 556K
    代理商： 550AE155M520BGR
    Si550
    2
    Rev. 0.5
    1. Electrical Specifications
    Table 1. Recommended Operating Conditions
    Parameter
    Symbol
    Test Condition
    Min
    Typ
    Max
    Units
    Supply Voltage1
    VDD
    3.3 V option
    2.97
    3.3
    3.63
    V
    2.5 V option
    2.25
    2.5
    2.75
    1.8 V option
    1.71
    1.8
    1.89
    Supply Current
    IDD
    Output enabled
    LVPECL
    CML
    LVDS
    CMOS
    —
    120
    108
    99
    90
    130
    117
    108
    98
    mA
    TriState mode
    —
    60
    70
    Output Enable (OE)2
    VIH
    0.75 x VDD
    ——
    V
    VIL
    ——
    0.5
    Operating Temperature Range3
    TA
    –40
    —
    85
    C
    Notes:
    1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
    2. OE pin includes a 17 k
    pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
    3. If the device is powered up below –20 C and the ambient temperature rises by approximately 105 C during normal
    operation, the device will perform a one-time recalibration. The output is squelched for approximately 2–3 ms during
    this recalibration.
    Table 2. VC Control Voltage Input
    Parameter
    Symbol
    Test Condition
    Min
    Typ
    Max
    Units
    Control Voltage Tuning Slope1,2,3
    KV
    10 to 90% of VDD
    —45
    90
    135
    180
    —
    ppm/V
    Control Voltage Linearity4
    LVC
    BSL
    –5
    ±1
    +5
    %
    Incremental
    –10
    ±5
    +10
    Modulation Bandwidth
    BW
    9.3
    10.0
    10.7
    kHz
    VC Input Impedance
    ZVC
    500
    —
    k
    Nominal Control Voltage
    VCNOM
    @ fO
    —3/8 x VDD
    —V
    Control Voltage Tuning Range
    VC
    0VDD
    V
    Notes:
    1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 7.
    2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
    requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
    3. KV variation is ±28% of typical values.
    4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
    determined with VC ranging from 10 to 90% of VDD.
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
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