- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67319 > 5504-CGT AUDIO SINGLE CHIP RECEIVER, PQFP48 PDF資料下載
參數(shù)資料
| 型號： | 5504-CGT |
| 元件分類： | 接收器 |
| 英文描述： | AUDIO SINGLE CHIP RECEIVER, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 80K |
| 代理商： | 5504-CGT |
5504 DCR
Direct Conversion Receiver
2
FUNCTIONAL DESCRIPTION
AGC Amplifier
The 5504 RF input can be driven differentially or
single ended. The RFp and RFn inputs are self-
biasing and are designed to be driven from a 50
Ohm source. For single-ended operation, the RFn
pin should be AC coupled to analog ground. A gain
control input, AGC, provides a 25 dB gain variation
with 0V providing minimum gain and 4V providing
maximum gain.
I/Q Mixer
The AGC amplifier drives the RF port of two identical
double balanced mixers.
The LO ports of these
mixers are driven from an on-chip quadrature
network.
Low Pass Filtering and Buffering
Following each mixer, a buffer amplifier is provided
for driving an external passive low-pass filter. The
nominal output impedance for IO1 and Q01 is 50
ohms. A second high impedance buffer amplifier is
provided (IIN or QIN) for additional gain and isolation
after the filter. The figure below shows a typical filter
designed for 20 Megasymbol per second operation:
Dual VCO
The 5504 uses two VCOs to cover the entire
specified tuning range.
Both VCOs use nearly
identical architecture with the only difference being
slight design modifications to optimize the range of
operation.
The lower range VCO requires an
external resonator that supports a tuning range of
950 to 1473 MHz. The higher range VCO requires a
similar resonator with inductor values designed to
support the range of 1390 to 2150 MHz. A typical
lumped-element
resonator
circuit
incorporating
varactor tuning is shown in the following figure:
Note: A separate resonator circuit is required for
each oscillator
PLL Synthesizer
The synthesizer derives its reference from a source
which can be either an externally derived clock or an
external crystal coupled to the internal oscillator.
This source drives a programmable reference divider
with 15 preset divide ratios from 2 to 320. This
divider output provides the PLL reference by driving
one input of a phase/frequency detector. The VCO
output drives a divider chain incorporating a variable
modulus
prescaler
and
divider.
The
divider
is
programmed by a 17-bit control word.
This divider
chain
output
drives
the
other
input
of
the
phase/frequency detector.
Loop Filter
The phase/frequency detector interface consists of
two ports, FILN and EON. The EON drives the base
of an external NPN transistor, and the FILN provides
a feedback path for the loop filter elements. The
external transistor permits VCO tune voltages of
greater than 30V and also provides the final stage of
the loop amplifier.
Below is shown a typical loop
filter:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5560/BEA | 0.04 A SWITCHING CONTROLLER, 100 kHz SWITCHING FREQ-MAX, CDIP16 |
| 5560/BEA | 0.04 A SWITCHING CONTROLLER, 100 kHz SWITCHING FREQ-MAX, CDIP16 |
| 5610-CG | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 567/BCA | PHASE LOCKED LOOP, 0.5 MHz, CDIP14 |
| 567/BCA | PHASE LOCKED LOOP, 0.5 MHz, CDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5504DCR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Direct Conversion Receiver |
| 5504F1-09P-01-03 | 制造商:SPC Multicomp 功能描述:PLUG D PCB R/A 9 WAY BL |
| 5504F1-09P-01-03-F1 | 制造商:SPC Multicomp 功能描述:PLUG D PCB R/A 9WAY |
| 5504F1-09P-02-03 | 制造商:SPC Multicomp 功能描述:PLUG D PCB R/A 9 WAY |
| 5504F1-09P-02-03-F1 | 制造商:SPC Multicomp 功能描述:CONNECTOR D-SUB PLUG THT R/A 9WAY 制造商:SPC Multicomp 功能描述:PLUG, D, PCB, R/A, 9WAY 制造商:PRIVATE LABEL 功能描述:CONNECTOR, D-SUB, PLUG, THT, R/A, 9WAY, Product Range:MULTICOMP - Dsub Formed Pi |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。