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參數(shù)資料
| 型號(hào)： | 54SX08A-3 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大小： | 92K |
| 代理商： | 54SX08A-3 |
2
S DRAM C ont r o l l e r S DRA M S i gn al
F unc t i on
The Controller connects to the SDRAM as expected. The
CASn, RASn, and WEn signals connect as expected. The
DQM signal from the controller may need to be connected to
multiple DQM lines depending on the width of SDRAM being
used.
There are two CSn lines: CS0N and CS1n.
The
assumption is that a user may want two banks (twice as
much address space) of SDRAMs. The CS0n then drives the
lower bank and the CS1n signal drives the upper bank of
SDRAMs. If only one bank is desired, connect the CS0n line
and leave the CS1n line unconnected. Some SDRAMS have
only two banks and require only one BA line. Most SDRAMS
have four banks and require two BA lines. When using a
small SDRAM, leave the BA1 line disconnected.
S DRAM C onf i g ur at i o n s f o r Va r i ous
S i ze s of S DRAMS
Inside the SDRAM Controller HDL code file are constants or
generic statements that allow the use of various sizes of
SDRAMs. The following constants or generics are included -
COL_WIDTH, ROW_WIDTH, BANK BITS AND CHIP BITS.
These constants configure the controller to fit a particular
SDRAM. COL_WIDTH defines the number of address bits
required to address all of the columns in the SDRAM.
ROW_WIDTH defines the number of address bits required to
address all of the rows in the SDRAM. The bank bits are the
address bits required to address the banks in the SDRAM.
The CHIP_BITS are the bits required to address the number
of banks in the SDRAM.
A typical application would be interfacing with one bank of
MT48??? SDRAMs. This is a 2Mx32x4banks SDRAM and the
settings are as follows:
ROW_WIDTH = 11
COL_WIDTH = 8
BANK BITS = 2
CHIP_BITS = 0
Te st be nc h
The test bench is defined in the system.vhd file and is
comprised of the following elements:
The SDRAM controller
A model of a Micron SDRAM
A test vector generator
The testbench causes the SDRAM controller to write and
then read/verify linear bursts of ten addresses to/from
various places in memory. During the first read write burst
(from time 100 us to 108 us), three bursts are written and
then
read/verified.
During
these
first
bursts,
RD/WR_BE_NOW are always asserted.
From time 116us to 118us, a read burst and a write burst are
executed with minimal deassertion of RD/WR_BE_NOW.
These bursts are designed to demonstrate the operation of
WR_BE_RDY
This signal indicates that the controller has readied the SDRAM for (to receive/accept?) data on the
following cycle. These signals are pipelined to give the user 1 clock cycle advanced warning of the
SDRAM’s readiness to accept data.
RD_BE_RDY
This signal indicates that the controller has readied the SDRAM to deliver data to the system on
the following cycle. These signals are pipelined to give the user 1 clock cycle advanced warning of
the SDRAM’s readiness to deliver data.
Outputs to the SDRAM
CS0n
Chip Select for low bank.
CS1n
Chip Select for upper (optional) bank.
RASn
This is the Ras signal.
CASn
This is the Cas signal.
WEn
This is the We signal.
BA0
This is the Bank 0 bit signal.
BA1
This is the Bank 1 (if used) signal.
MADDR(N:0)
This is the multiplexed RAS / CAS address bus.
DQM
This is the Data mask signal.
CKE
This is the Clock enable signal.
Table 1 SDRAM Controller Signals
Name
Description
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| 54SX08-STD | Controller Miscellaneous - Datasheet Reference |
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