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參數資料
| 型號： | 5429FCT52DTD |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | LM140L/LM340L Series 3-Terminal Positive Regulators; Package: TO-39; No of Pins: 3; Qty per Container: 20; Container: Tray |
| 中文描述： | 快速CMOS八進制注冊收發(fā)器 |
| 文件頁數： | 7/8頁 |
| 文件大?。?/td> | 125K |
| 代理商： | 5429FCT52DTD |
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.1
7
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
PROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Pulse
Generator
R T
D.U.T.
V CC
VIN
C L
VOUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
CL=
Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2629 lnk 12
2629 drw 03
2629 drw 04
2629 drw 05
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
2629 drw 07
2629 drw 06
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