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    參數(shù)資料
    型號(hào): 531AA525M000BGR
    廠商: SILICON LABORATORIES
    元件分類: XO, clock
    英文描述: CRYSTAL OSCILLATOR, CLOCK, 525 MHz, LVPECL OUTPUT
    封裝: ROHS COMPLIANT, SMD, 6 PIN
    文件頁(yè)數(shù): 9/15頁(yè)
    文件大?。?/td> 268K
    代理商: 531AA525M000BGR
    Si530/531
    Rev. 1.0
    3
    Table 3. CLK± Output Levels and Symmetry
    Parameter
    Symbol
    Test Condition
    Min
    Typ
    Max
    Units
    LVPECL Output Option1
    VO
    mid-level
    VDD – 1.42
    VDD – 1.25
    V
    VOD
    swing (diff)
    1.1
    1.9
    VPP
    VSE
    swing (single-ended)
    0.5
    0.93
    VPP
    LVDS Output Option2
    VO
    mid-level
    1.125
    1.20
    1.275
    V
    VOD
    swing (diff)
    0.32
    0.40
    0.50
    VPP
    CML Output Option2
    VO
    mid-level
    VDD – 0.75
    V
    VOD
    swing (diff)
    0.70
    0.95
    1.20
    VPP
    CMOS Output Option3
    VOH
    IOH =32mA
    0.8 x VDD
    VDD
    V
    VOL
    IOL =32mA
    0.4
    Rise/Fall time (20/80%)
    tR, tF
    LVPECL/LVDS/CML
    350
    ps
    CMOS with CL = 15 pF
    1
    ns
    Symmetry (duty cycle)
    SYM
    LVPECL:
    VDD – 1.3 V (diff)
    LVDS:
    1.25 V (diff)
    CMOS:
    VDD/2
    45
    55
    %
    Notes:
    1. 50
    to VDD – 2.0 V.
    2. Rterm = 100 (differential).
    3. CL = 15 pF
    Table 4. CLK± Output Phase Jitter
    Parameter
    Symbol
    Test Condition
    Min
    Typ
    Max
    Units
    Phase Jitter (RMS)*
    for FOUT > 500 MHz
    φ
    J
    12 kHz to 20 MHz (OC-48)
    0.40
    0.50
    ps
    50 kHz to 80 MHz (OC-192)
    LVPECL
    CML
    LVDS
    0.30
    0.35
    0.40
    0.47
    0.49
    ps
    Phase Jitter (RMS)*
    for FOUT of 125 to 500 MHz
    φ
    J
    12 kHz to 20 MHz (OC-48)
    LVPECL
    CML
    LVDS
    0.40
    0.45
    0.50
    0.52
    ps
    *Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
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