參數(shù)資料
型號(hào): 530GB622M080BGR
廠商: Silicon Laboratories Inc.
英文描述: CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)
中文描述: 晶體振蕩器(XO)(10 MHz至1.4 GHz)
文件頁數(shù): 4/10頁
文件大?。?/td> 173K
代理商: 530GB622M080BGR
Si530/531
Preliminary Rev. 0.4
3
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVPECL Output Option1
VO
mid-level
VDD – 1.42
VDD – 1.25
V
VOD
swing (diff)
1.1
1.9
VPP
VSE
swing (single-ended)
0.5
0.93
VPP
LVDS Output Option2
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.32
0.40
0.50
VPP
CML Output Option2
VO
mid-level
VDD – 0.75
V
VOD
swing (diff)
0.70
0.95
1.20
VPP
CMOS Output Option3
VOH
IOH =32mA
0.8 x VDD
VDD
V
VOL
IOL =32mA
0.4
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
350
ps
CMOS with CL = 15 pF
1
ns
Symmetry (duty cycle)
SYM
LVPECL:
VDD – 1.3 V (diff)
LVDS:
1.25 V (diff)
CMOS:
VDD/2
45
55
%
Notes:
1. 50
to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
Table 4. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Phase Jitter (RMS)*
for FOUT > 500 MHz
φJ
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
0.27
0.30
ps
Phase Jitter (RMS)*
for FOUT of 125 to 500 MHz
φ
J
12 kHz to 20 MHz (OC-48)
0.50
ps
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Table 5. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Period Jitter*
for FOUT < 160 MHz
JPER
RMS
1
ps
Peak-to-Peak
5
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
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