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參數(shù)資料
| 型號： | 5270 |
| 廠商： | Aeroflex Inc. |
| 元件分類： | 64位微處理器 |
| 英文描述： | ACT5270 64-Bit Superscaler Microprocessor |
| 中文描述： | ACT5270 64位微處理器Superscaler |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 160K |
| 代理商： | 5270 |
Features
I
Full militarized QED RM5270 microprocessor
I
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
G
133, 150, 200 MHz operating frequencies – Consult Factory for
latest speeds
G
260 Dhrystone2.1 MIPS
G
SPECInt95 5.0, SPECfp95 5.3
eroflex Circuit Technology – RISC TurboEngines For The Future SCD5270 REV 1 12/22/98
BLOCK DIAGRAM
I
High performance system interface compatible with RM5260,
R4600, R4700 and R5000
G
64-bit multiplexed system address/data bus for optimum price/
performance with up to 100 MHz operating frequency
G
High performance write protocols maximize uncached write
bandwidth
G
Supports clock divisors (2, 3, 4, 5, 6, 7, 8)
G
5V compatible I/O’s
G
IEEE 1149.1 JTAG boundary scan
I
Integrated on-chip caches
G
16KB instruction - 2 way set associative
G
16KB data - 2 way set associative
G
Virtually indexed, physically tagged
G
Write-back and write-through on per page basis
G
Pipeline restart on first double for data cache misses
I
Integrated memory management unit
G
Fully associative joint TLB (shared by I and D translations)
G
48 dual entries map 96 pages
G
Variable page size (4KB to 16MB in 4x increments)
I
Integrated secondary cache controller (R5000 compatible)
G
Supports 512K or 2MByte block write-through secondary
I
High-performance floating point unit
G
Single cycle repeat rate for common single precision operations
and some double precision operations
G
Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
G
Single cycle repeat rate for single precision combined multiply-
add operation
I
MIPS IV instruction set
G
Floating point multiply-add instruction increases performance in
signal processing and graphics applications
G
Conditional moves to reduce branch frequency
G
Index address modes (register + register)
I
Embedded application enhancements
G
Specialized DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
G
I and D cache locking by set
G
Optional dedicated exception vector for interrupts
I
Fully static CMOS design with power down logic
G
Standby reduced power mode with WAIT instruction
G
6 Watts typical at 3.3V 200 MHz
I
208-lead CQFP, cavity-up package (F17)
I
208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
I
179-pin PGA package (Future Product) (P10)
Preliminary
64-Bit Superscaler Microprocessor
ACT5270
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