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參數(shù)資料
| 型號(hào)： | 522940B |
| 英文描述： | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 中文描述： | 集成電路 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | 522940B |
6
LTC1451
LTC1452/LTC1453
GND:
Ground.
REF:
The Output of the Internal Reference and the Input
to the DAC Resistor Ladder. An external reference with
voltage up to V
CC
/2 may be used for the LTC1452.
V
OUT
:
The Buffered DAC Output.
V
CC
:
The Positive Supply Input. 4.5V
≤
V
CC
≤
5.5V
(LTC1451), 2.7
≤
V
CC
≤
5.5V (LTC1452/LTC1453). Re-
quires a bypass capacitor to ground.
CLK:
The TTL Level Input for the Serial Interface Clock.
D
IN
:
The TTL Level Input for the Serial Interface Data. Data
on the D
IN
pin is latched into the shift register on the rising
edge of the serial clock.
CS/LD:
The TTL Level Input for the Serial Interface Enable
and Load Control. When CS/LD is low the CLK signal is
enabled, so the data can be clocked in. When CS/LD is
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.
D
OUT
:
The Output of the Shift Register which Becomes
Valid on the Rising Edge of the Serial Clock.
B11
MSB
B10
t
1
t
9
B1
t
6
B0
LSB
B11
CURRENT WORD
t
7
t
2
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1451/2/3 TD
B0
PREVIOUS WORD
B11
PREVIOUS WORD
B10
B1
B0
DAC
REGISTER
LD
+
–
REFERENCE
LTC1451: 2.048V
LTC1453: 1.22V
12-BIT
SHIFT
REGISTER
POWER-ON
RESET
11451/2/3 BD
CLK 1
D
IN
2
D
OUT
4
V
OUT
7
REF
6
GND
5
V
CC
8
3
CS/LD
12-BIT DAC
PIU
BLOCK DIAGRA
TIW
W
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