參數(shù)資料
型號： DSPIC30F4013-30I/P
廠商： Microchip Technology
文件頁數(shù)： 98/153頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 48K 40DIP
產(chǎn)品培訓(xùn)模塊： Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝： 10
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： AC'97，欠壓檢測/復(fù)位，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 30
程序存儲器容量： 48KB（16K x 24）
程序存儲器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： AC30F003-ND - MODULE SOCKET DSPIC30F 40DIP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
其它名稱： DSPIC30F4013-30IP
2010 Microchip Technology Inc.
DS70138G-page 49
dsPIC30F3014/4013
6.0
DATA EEPROM MEMORY
The data EEPROM memory is readable and writable
during normal operation over the entire VDD range. The
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory as well. As described in Section 5.5 “Control
Registers”, these registers are:
NVMCON
NVMADR
NVMADRU
NVMKEY
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR, in conjunction with the
NVMADRU
register,
are
used
to
address
the
EEPROM location being accessed. TBLRDL and
TBLWTL
instructions are used to read and write data
EEPROM. The dsPIC30F devices have up to 8 Kbytes
(4K words) of data EEPROM with an address range
from 0x7FF000 to 0x7FFFFE.
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
varies with voltage and temperature.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
Control bit, WR, initiates write operations similar to
program Flash writes. This bit cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the write operation. The inability to clear
the WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, allows a write operation. On
power-up, the WREN bit is clear. The WRERR bit is set
when a write operation is interrupted by a MCLR Reset
or a WDT Time-out Reset during normal operation. In
these situations, following Reset, the user can check
the WRERR bit and rewrite the location. The address
register, NVMADR, remains unchanged.
6.1
Reading the Data EEPROM
A TBLRD instruction reads a word at the current
program word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4 as shown in Example 6-1.
EXAMPLE 6-1:
DATA EEPROM READ
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s
Reference
Manual”
(DS70157).
Note:
Interrupt flag bit, NVMIF in the IFS0 regis-
ter, is set when the write is complete. It
must be cleared in software.
MOV
#LOW_ADDR_WORD,W0
; Init Pointer
MOV
#HIGH_ADDR_WORD,W1
MOV
W1,TBLPAG
TBLRDL
[ W0 ], W4
; read data EEPROM
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