參數(shù)資料
型號(hào)： 4N46#500
廠商： AGILENT TECHNOLOGIES INC
元件分類： 光電耦合器
英文描述： 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER
封裝： SURFACE MOUNT PACKAGE-6
文件頁(yè)數(shù)： 6/9頁(yè)
文件大小： 141K
代理商： 4N46#500
6
VCC = 5 V
Figure 5. Current Transfer Ratio vs.
Input Current.
Figure 6. Propagation Delay vs.
Forward Current.
Figure 7. Propagation Delay vs.
Temperature.
Notes:
1. Derate linearly above 50
°C free-air
temperature at a rate of 0.4 mA/
°C.
2. Derate linearly above 50
°C free-air
temperature at a rate of 0.7 mW/
°C.
3. Derate linearly above 25
°C free-air
temperature at a rate of 0.8 mA/
°C.
4. Derate linearly above 25
°C free-air
temperature at a rate of 1.5 mW/
°C.
5. DC CURRENT TRANSFER RATIO is
defined as the ratio of output
collector current, IO, to the forward
LED input current, IF, times 100%.
6. Pin 6 Open.
Package Characteristics
For 0
°C ≤ T
A ≤ 70°C, unless otherwise specified. All typicals at TA = 25°C.
Parameter
Symbol
Min.
Typ.
Max. Units
Test Conditions
Fig.
Notes
Input-Output Momentary
VISO
3750
V rms
RH
≤ 50%, t = 1 min,
7, 10
Withstand Voltage*
TA = 25°C
Resistance, Input-Output
RI-O
1012
VI-O = 500 Vdc
7
Capacitance, Input-Output
CI-O
0.6
pF
f = 1 MHz
7
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification, or Agilent Application Note 1074, “Optocoupler Input-Output Endurance Voltage.”
maximum tolerable (negative)
dVcm/dt on the trailing edge of the
common mode pulse signal, Vcm, to
assure that the output will remain in
a Logic Low state (i.e., VO < 2.5 V).
10. In accordance with UL 1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 4500 V rms for 1 second (leakage
detection current limit, II-O ≤ 5 A).
7. Device considered a two-terminal
device: Pins 1, 2, 3 shorted together
and Pins 4, 5, and 6 shorted together.
8. Use of a resistor between pin 4 and 6
will decrease gain and delay time.
(See Figures 11, 12, and 13.)
9. Common mode transient immunity in
Logic High level is the maximum
tolerable (positive) dVcm/dt on the
leading edge of the common mode
pulse, VCM, to assure that the output
will remain in a Logic High state (i.e.,
VO > 2.5 V). Common mode transient
immunity in Logic Low level is the
Figure 2. Input Diode Forward
Current vs. Forward Voltage.
Figure 3. Typical DC Transfer
Characteristics.
Figure 4. Output Current vs. Input
Current.
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