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參數(shù)資料
| 型號： | 48F4267 |
| 英文描述： | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 中文描述： | 晶體管場效應(yīng)管- 220 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 216K |
| 代理商： | 48F4267 |
1
Motorola, Inc. 1996
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS E–FET
MAXIMUM RATINGS
(TC = 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60
Vdc
Drain–to–Gate Voltage (RGS = 1.0 M
)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage
— Non–repetitive (tp
≤
10 ms)
Drain Current — Continuous
Drain Current
— Continuous @ 100
°
C
Drain Current
— Single Pulse (tp
≤
10
μ
s)
Total Power Dissipation
Derate above 25
°
C
60
Vdc
±
15
±
25
Vdc
Vpk
15
12
53
Adc
Apk
60
0.40
Watts
W/
°
C
Operating and Storage Temperature Range
TJ, Tstg
EAS
–55 to 175
°
C
mJ
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25
°
C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25
)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
113
R
θ
JC
R
θ
JA
TL
2.5
62.5
°
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″
from case for 10 seconds
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
260
°
C
REV 1
Order this document
by MTP15N06VL/D
SEMICONDUCTOR TECHNICAL DATA
TM
D
S
G
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.085 OHM
CASE 221A–06, Style 5
TO–220AB
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