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參數(shù)資料
| 型號(hào)： | 4302-52 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | 衰減器 |
| 英文描述： | 50 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ |
| 中文描述： | 0 MHz - 4000 MHz RF/MICROWAVE VARIABLE ATTENUATOR, 1.75 dB INSERTION LOSS-MAX |
| 封裝： | 4 X 4 MM, GREEN, QFN-20 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 469K |
| 代理商： | 4302-52 |
Product Specification
PE4302
Page 5 of 11
Document No. 70-0056-04
│ www.psemi.com
2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Table 2. Pin Descriptions
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 3.
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Note 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 k
resistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 k
resistor in series, as close to pin as possible to
avoid frequency resonance.
Figure 14. Pin Configuration (Top View)
V
DD
PUP1
PUP2
V
DD
GN
D
1
20
19
18
17
16
15
14
13
12
11
6
7
8
9
10
2
3
4
5
C16
RF1
Data
Clock
LE
GND
Vss/GND
P/S
RF2
C8
C4
C2
GN
D
C1
C0
.5
20-lead QFN
4x4mm
Exposed Solder Pad
Pin
No.
Pin
Name
Description
1
C16
Attenuation control bit, 16dB (Note 4).
2
RF1
RF port (Note 1).
3
Data
Serial interface data input (Note 4).
4
Clock
Serial interface clock input.
5
LE
Latch Enable input (Note 2).
6
VDD
Power supply pin.
7
PUP1
Power-up selection bit, MSB.
8
PUP2
Power-up selection bit, LSB.
9
VDD
Power supply pin.
10
GND
Ground connection.
11
GND
Ground connection.
12
Vss/GND
Negative supply voltage or GND
connection(Note 3)
13
P/S
Parallel/Serial mode select.
14
RF2
RF port (Note 1).
15
C8
Attenuation control bit, 8 dB.
16
C4
Attenuation control bit, 4 dB.
17
C2
Attenuation control bit, 2 dB.
18
GND
Ground connection.
19
C1
Attenuation control bit, 1 dB.
20
C0.5
Attenuation control bit, 0.5 dB.
Paddle
GND
Ground for proper operation
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS de-
vices are immune to latch-up.
Switching Frequency
The PE4302 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 k
resistor on the inputs to Pin 1 & 3 (see Figure
16) will eliminate package resonance between the RF
input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Table 3. Absolute Maximum Ratings
Table 4. Operating Ranges
Symbol
Parameter/Conditions
Min
Max
Units
VDD
Power supply voltage
-0.3
4.0
V
VI
Voltage on any DC input
-0.3
VDD+
0.3
V
TST
Storage temperature range
-65
150
°C
P
IN
Input power (50
)
+30
dBm
VESD
ESD voltage (Human Body
Model)
500
V
Parameter
Min
Typ
Max
Units
VDD Power Supply
Voltage
2.7
3.0
3.3
V
IDD Power Supply
Current
100
A
Digital Input High
0.7xVDD
V
Digital Input Low
0.3xVDD
V
Digital Input Leakage
1
A
Input Power
+24
dBm
Temperature range
-40
85
°C
Exceeding absolute maximum ratings may cause per-
manent damage. Operation should be restricted to the
limits in the Operating Ranges table. Operation be-
tween operating range maximum and absolute maxi-
mum for extended periods may reduce reliability.
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