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參數(shù)資料
| 型號(hào)： | 4099B |
| 英文描述： | 8-BIT ADDRESSABLE LATCH(302.59 k) |
| 中文描述： | 8位可尋址閉鎖（302.59十一） |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 302K |
| 代理商： | 4099B |
HCC/HCF4099B
September 1988
8-BIT ADDRESSABLE LATCH
.
SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
.
STORAGEREGISTER CAPABILITY - MASTER
CLEAR
.
CAN FUNCTIONAS DEMULTIPLEXER
.
STANDARDIZED
CHARACTERISTICS
.
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
.
5V, 10V, AND 15V PARAMETRIC RATINGS
.
INPUT CURRENTOF100nA AT18V AND25
°
C
FOR HCC DEVICE
.
100% TESTEDFOR QUIESCENTCURRENT
.
MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVE STANDARD N
°
. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
SYMMETRICAL
OUTPUT
DESCRIPTION
The
HCC4099B
(extended temperature range) and
HCF4099B
(intermediate temperature range) are
monolithicintegratedcircuits,available in16-leaddual
in-line plastic or ceramic package and plastic micro
package. The HCC/HCF4099B 8-bit addressable
latchisaserial-input, parallel-output storageregister
that can perform a variety of functions. Data are in-
putted to a particular bit inthe latch when that bit is
addressed (by means of inputs A0, A1, A2) and
when WRITE DISABLE is at a low level. When
WRITE DISABLE is high, data entry is inhibited ;
however, all 8 outputs can be continuously readin-
dependent of WRITEDISABLE andaddress inputs.
A masterRESET input is available, which resets all
bits to a logic ”0” level when RESET and WRITE
DISABLE are at a high level. When RESET is at a
highlevel, and WRITEDISABLE isatalowlevel,the
latch acts as a 1-of-8 demultiplexer ; the bit that is
addressed has an active output which follows the
data input, while all unaddressed bits are held to a
logic ”0” level.
ORDER CODES
:
HCC4099BF
HCF4099BEY
HCF4099BM1
HCF4099BC1
M1
Micro Package
C1
Plastic ChipCarrier
EY
Plastic Package
F
Ceramic Frit SealPackage
PIN CONNECTIONS
1/14
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