
4066
CMOS
IC
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
5 of 7
QW-R502-009,C
S PECIAL CONS IDERAT IONS
In applications where separate power sources are used to drive V
DD
and the signal input, the V
DD
current capability
should exceed V
DD
/R
L
(R
L
=effective external load of the UTC
4066
bilateral switches).This provision avoids any
permanent current flow or clamp action of the V
DD
supply when power is applied or removed from UTC 4066.
In certain applications, the external load-resistor current may include both V
DD
and Signal-line components. To
avoid drawing V
DD
current when switch current flows into terminals 1,4,8 or 11,the voltage drop across the
bidirectional swith must not exceed 0.6V at Ta
≤
25
, or 0.4V at Ta >25
NO V
DD
current will flow through R
L
if the switch current flows into terminals2, 3, 9 or 10.
(calculated from R
ON
values shown).
AC T ES T CIRCUIT S AND S WIT CHING T IME WAV EFORMS
V
C
=V
DD
V
IS
V
DD
V
OS
R
L
200K
C
L
50pF
90%
50%
10%
V
DD
0V
V
DD
0V
V
OS
V
IS
tf
tf
t
PLN
t
PNL
50%
FIGURE 1. t
PHL
, t
PLH
Propagation Delay Time Signal Input to Signal Output
CONTROL
V
DD
IN/OUT
Vss
1 OF 4
SWITCHES
OT/IN
V
C
V
DD
V
OS
R
L
1K
50%
10%
V
DD
0V
V
OH
0V
t
PHZ
FIGURE 2. t
PZH
, t
PHZ
Propagation Delay Time Control to Signal Output
V
IS
=V
DD
t
PZH
V
DD
0V
V
OH
0V
50%
90%
V
DD
t
PZH
t
PHZ
C
L
50pF
CONTROL
V
DD
IN/OUT
OUT/IN
Vss
1 OF 4
SWITCHES
CONTROL
V
DD
IN/OUT
OUT/IN
Vss
1 OF 4
SWITCHES
V
C
V
DD
V
OS
R
L
1K
50%
V
DD
0V
V
DD
V
OL
t
PLZ
FIGURE 3. t
PZL
, t
PLZ
Propagation Delay Time Control to Signal Output
V
IS
=0V
t
PZL
V
DD
0V
50%
t
PZL
t
PLZ
V
DD
90%
10%
V
DD
V
OL
C
50pF
V
C
5V
V
OS
R
L
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
V
IS
-5V
Vc=V
for distortion and frequency response tests
Vc=Vss for feedthrough test
CONTROL
V
DD
IN/OUT
OUT/IN
Vss
1 OF 4
SWITCHES
1/ f
2.5V
V
IS
0V
-2.5V
=