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參數(shù)資料
| 型號： | 40430A |
| 英文描述： | 4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor |
| 中文描述： | 4kbit的EEPROM，三電壓監(jiān)視器集成CPU監(jiān)控 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 421K |
| 代理商： | 40430A |
X40430/X40431 – Preliminary Information
Characteristics subject to change without notice.
3 of 24
REV 1.2.3 11/28/00
www.xicor.com
8
SDA
Serial Data.
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH prevents writes to any location in the device (including all the registers).
It has an internal pull down resistor.
V3 Voltage Monitor Input.
When the V3MON input is less than the V
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a third power supply with no external components. Connect V3MON to V
not used.
V3 Voltage Fail Output.
This open drain output goes LOW when V3MON is less than V
goes HIGH when V3MON exceeds V
TRIP3
. There is no power up reset delay circuitry on this pin.
WDO Output.
WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
SDA is a bidirectional pin used to transfer data into and out of the device. It has an
9
10
SCL
WP
11
V3MON
TRIP3
voltage, V3FAIL goes
SS
or
V
CC
when
12
V3FAIL
TRIP3
and
13
WDO
14
V
CC
Supply Voltage
PIN DESCRIPTION
(Continued)
Pin
Name
Function
PRINCIPLES OF OPERATION
Power On Reset
Applying power to the X40430/31 activates a Power
On Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
CC
exceeds the device V
for t
PURST
(selectable) the circuit releases the RESET
(X40431) and RESET (X40430) pin allowing the system
to begin operation.
TRIP1
threshold value
Figure 1. Connecting a Manual Reset Push-Button
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for t
after.
PURST
there-
V
CC
MR
System
Reset
Manual
Reset
X40430
RESET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 40430B | 4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor |
| 4043B | Quadruple R/S latch with 3-state outputs |
| 4044-UCA | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 4044-UCB | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 40430B | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor |
| 40430C | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor |
| 40430X | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor |
| 404310 | 制造商:MAGNUM / COOPER 功能描述: |
| 40431-0010 | 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:MS4800-ADPT-TXS |
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