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參數(shù)資料
| 型號(hào)： | 4015B |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output |
| 中文描述： | CMOS雙4級(jí)靜態(tài)移位寄存器在串行輸入/并行輸出 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 118K |
| 代理商： | 4015B |
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Ofce Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Specications CD4015BMS
Logic Diagram
FIGURE 1. CD4015BMS LOGIC DIAGRAM
TRUTH TABLE
CL
D
R
Q1
Qn
0
Qn-1
1
0
1
Qn-1
X
0
Q1
Qn
(No Change)
XX
1
0
X = Don’t care Case
DQ
Q
CL
R
p
n
CL
D
DQ
CL Q
R
CL
Q
DQ
Q
CL
R
DQ
Q
CL
R
DQ
Q
CL
R
p
n
CL
p
n
CL
p
n
CL
VDD
VSS
CL
R
Q
13
Q1
(5)
12
Q2
(4)
11
Q3
(3)
2
Q4
(10)
15
DATA
(7)
*
1
CLOCK
(9)
*
14
RESET
(6)
*
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
≡
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