參數(shù)資料
型號: 3D7608
廠商: Data Delay Devices, Inc.
英文描述: 8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS
中文描述: 8位
文件頁數(shù): 3/7頁
文件大?。?/td> 186K
代理商: 3D7608
Doc #06009
5/8/2006
3D7608 & 3D7612
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
APPLICATION NOTES (CONT’D)
TRIGGER & RESET TIMING
Figure 2 shows the timing diagram of the device
when the reset input (RES) is not used. In this
case, the pulse is triggered by the rising edge of
the TRIG signal and ends at a time determined
by the address loaded into the device. While the
pulse is active, any additional triggers occurring
are ignored. Once the pulse has ended, and after
a short recovery time, the next trigger is
recognized. Figure 3 shows the timing for the
case where a reset is issued before the pulse
has ended. Again, there is a short recovery time
required before the next trigger can occur.
ADDRESS UPDATE
The 3D7608/3D7612 can operate in one of two
addressing modes. In the transparent mode (AE
held high), the parallel address inputs must
persist for the duration of the output pulse, in
accordance with Figure 4. In the latched mode,
the address data is stored internally, which
allows the parallel inputs to be connected to a
multi-purpose data bus. Timing for this mode is
also shown in Figure 4.
8- OR 12-BIT LATCH
AE
TRG
ADDR ENABLE
TRIGGER
PULSE OUT
Figure 1: Functional block diagram
OUT
OUTB
RES
RESET
DELAY
LINE
OSCILLATOR/
COUNTER
INPUT
LOGIC
OUTPUT
LOGIC
P0
P7
P11
P10
P9
P8
P1
BIT-SHIFT LOGIC
TRIG
Figure 2: Timing Diagram (RES=0)
t
TW
t
RTO
t
ID
t
PW
OUT
OUTB
TRIG
Figure 3: Timing Diagram (with reset)
t
TW
t
RTR
t
ID
t
RD
OUT
OUTB
RES
t
RW
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