參數(shù)資料
型號： 3886GROUP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 99/110頁
文件大?。?/td> 1601K
代理商： 3886GROUP
99
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Note:
The RESET
OUT
output goes “H” in synchronized with the rise of the
φ
clock that is anywhere between a few cycles and 10-several cycles after RESET
input goes “H”.
Table 46 Timing requirements in memory expansion mode and microprocessor mode
(V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, T
a
= –20 to 85 °C, in high-speed mode, unless otherwise noted)
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
t
su
(ONW-
φ
)
t
h
(
φ
-ONW)
t
su
(DB-
φ
)
t
h
(
φ
-DB)
t
su
(ONW-RD), t
su
(ONW-WR)
t
h
(RD-ONW), t
h
(WR-ONW)
t
su
(DB-RD)
t
h
(RD-DB)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
–20
–20
50
0
–20
–20
50
0
Typ.
Max.
Symbol
Unit
Table 47 Switching characteristics in memory expansion mode and microprocessor mode
(V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, T
a
= –20 to 85 °C, in high-speed mode, unless otherwise noted)
φ
clock cycle time
φ
clock “H” pulse width
φ
clock “L” pulse width
AD
15
–AD
8
delay time
AD
7
–AD
0
delay time
AD
15
–AD
8
valid time
AD
7
–AD
0
valid time
SYNC delay time
SYNC valid time
Data bus delay time
Data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(When one-wait is valid)
AD
15
–AD
8
delay time
AD
7
–AD
0
delay time
AD
15
–AD
8
valid time
AD
7
–AD
0
valid time
Data bus delay time
Data bus valid time
RESET
OUT
output delay time
RESET
OUT
output valid time
(Note)
t
C
(
φ
)
t
WH
(
φ
)
t
WL
(
φ
)
t
d
(
φ
-AH)
t
d
(
φ
-AL)
t
V
(
φ
-AH)
t
V
(
φ
-AL)
t
d
(
φ
-SYNC)
t
V
(
φ
-SYNC)
t
d
(
φ
-DB)
t
V
(
φ
-DB)
t
WL
(RD), t
WL
(WR)
t
d
(AH-RD), t
d
(AH-WR)
t
d
(AL-RD), t
d
(AL-WR)
t
V
(RD-AH), t
V
(WR-AH)
t
V
(RD-AL), t
V
(WR-AL)
t
d
(WR-DB)
t
V
(WR-DB)
t
d
(RESET-RESET
OUT
)
t
V
(
φ
-RESET
OUT
)
Limits
Parameter
Min.
Typ.
Max.
Symbol
Unit
Test
conditions
Fig. 83
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
C
(X
IN
)–10
t
C
(X
IN
)–10
2
2
10
t
C
(X
IN
)–10
3t
C
(X
IN
)–10
t
C
(X
IN
)–35
t
C
(X
IN
)–40
2
2
10
0
35
40
30
30
200
100
2t
C
(X
IN
)
16
20
5
5
16
5
15
t
C
(X
IN
)–16
t
C
(X
IN
)–20
5
5
15
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