參數(shù)資料
型號: 37LV128-P
廠商: Microchip Technology Inc.
英文描述: 36K, 64K, and 128K Serial EPROM Family
中文描述: 36K,64K的,和128K串行EPROM家庭
文件頁數(shù): 6/12頁
文件大小: 88K
代理商: 37LV128-P
37LV36/65/128
DS21109E-page 6
1996 Microchip Technology Inc.
TABLE 11-3:
PIN ASSIGNMENTS IN THE PROGRAMMING MODE
DIP/SOIC
Pin
PLCC Pin
Name
I/O
Description
1
2
DATA
I/O
The rising edge of the clock shifts a data word in or out of the
EPROM one bit at a time.
2
4
CLK
I
Clock Input. Used to increment the internal address/word
counter for reading and programming operation.
3
6
RESET/OE
I
The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
Note 1: Any modified polarity of the RESET/OE pin is
ignored in the programming mode.
4
8
CE
I
The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
5
10
V
SS
Ground pin.
6
14
CEO
O
The polarity of the RESET/OE pin can be read by sensing the
CEO pin.
Note 1: The polarity of the RESET/OE pin is ignored while in
the Programming Mode. In final verification, this pin
must be monitored to go LOW one clock cycle after
the last data bit has been read.
7
17
V
PP
Programming Voltage Supply. Programming Mode is entered
by holding CE and OE HIGH and V
PP
at V
PP
1 for two rising
clock edges and then lowering V
PP
to V
PP
2 for one more ris-
ing clock edge. A word is programmed by strobing the device
with V
PP
for the duration TPGM. V
PP
must be tied to V
CC
for
normal read operation.
8
20
V
CC
+5 V power supply input.
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