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參數(shù)資料
| 型號(hào)： | 3342-56 |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 0K |
| 描述： | IC PLL INTEGER-N 3GHZ 20QFN |
| 標(biāo)準(zhǔn)包裝： | 6,000 |
| 系列： | UltraCMOS™ |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | RF 儀表系統(tǒng)，無線基站 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 電源電壓： | 2.85 V ~ 3.15 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（4x4） |
| 包裝： | 帶卷 (TR) |
Product Specification
PE3342
Page 2 of 17
2005-8 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0091-04
│ UltraCMOS RFIC Solutions
Table 2. Pin Descriptions
Figure 2. Pin Configuration (Top View)
Figure 3. Package Type
20-lead QFN
Pin No.
Pin Name
Type
Description
1
S_WR
Input
Secondary Register WRITE input. Primary Register contents are copied to the Secondary Register on
S_WR rising edge. Also used to control Serial Port operation and EEPROM programming.
2
Data
Input
Binary serial data input. Input data entered LSB (B0) first.
3
Clock
Input
Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit EE Register, or
the 8-bit Enhancement Register on the rising edge of Clock. Also used to clock EE Register data out
Dout port.
4
FSel
Input
Frequency Register selection control line. Internal 70 kW pull-down resistor.
5
E_WR
Input
Enhancement Register write enable. Also functions as a Serial Port control line. Internal 70 kW pull-
down resistor.
6
VPP
Input
EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass capacitor connected
to GND.
7
VDD
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
8
Fin
Input
Prescaler input from the VCO.
9
Fin
Input
Prescaler complementary input. A series 50 W resistor and DC blocking capacitor should be placed as
close as possible to this pin and connected to the ground plane.
10
CEXT
Output
Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2 kW series resistor. Connecting
CEXT to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
11
EELoad
Input
Control line for Serial Data Port, Frequency Register selection, EE Register parallel loading, and
EEPROM programming. Internal 70 kW pull-down resistor.
12
LD
Output, OD
Lock detect output, an open-drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance; otherwise, LD is a logic LOW.
13
Dout
Output
Data out function. Dout is defined with the Enhancement Register and enabled with ENH.
14
VDD
(Note 1)
Same as pin 7.
19
VDD
(Note 1)
Same as pin 7.
20
ENH
Input
Enhancement mode control line. When asserted LOW, enhancement register bits are functional.
Internal 70 kW pull-up resistor.
15
PD_D
Output
Phase detector output. PD_D pulses negatively when fp leads fc.
16
PD_U
Output
Phase detector output. PD_U pulses negatively when fc leads fp.
17
EESel
Input
Control line for Frequency Register selection, EE Register parallel loading, and EEPROM
programming. Internal 70 kW pull-up resistor.
18
fr
Input
Reference frequency input.
V
PP
V
DD
F
IN
F
IN
C
EXT
1
20
19
18
17
16
15
14
13
12
11
6
7
8
9
10
2
3
4
5
20-lead QFN
4x4mm
Exposed Solder Pad
(Bottom Side)
S_WR
Data
Clock
FSel
E_WR
EELoad
LD
Dout
V
DD
PD_D
PD
_
U
E
ESe
l
f r
V
DD
EN
H
Notes 1: VDD pins 7, 14 and 19 are connected by diodes and must be supplied with the same positive voltage level.
2: Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation.
Obsolete
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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