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參數(shù)資料
| 型號(hào)： | 32C408BRPFS-20 |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | SRAM |
| 英文描述： | 4 Megabit (512K x 8-Bit) SRAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 20 ns, DFP36 |
| 封裝： | RAD PAK, LDFP-36 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 187K |
| 代理商： | 32C408BRPFS-20 |
M
6
All data sheets are subject to change without notice
2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) SRAM
32C408B
05.02.02 Rev 7
F
IGURE
2. T
IMING
W
AVEFORM
OF
W
RITE
C
YCLE
(OE L
OW
F
IXED
)
1. All write cycle timng is referenced fromthe last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and
WE going low: A write ends at the earliest transition among CS going high or WE going high. t
WP
is measured frombeginning
of write to end of write.
3. t
CW
is measured fromthe later of CS going low to end of write.
4. t
AS
is measured fromthe address valid to the beginning of write.
5. t
WR
is measured fromthe end of write to the address change. TWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, mnimzation or elimnation of bus contention conditions is necessary during read and write
cycle.
8. IC CS goes low simultaneously with WE going low or after WE going low the outputs remain high impedance state.
9. D
OUT
is the read data of the new address.
10.When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
F
IGURE
3. T
IMING
W
AVEFORM
OF
R
EAD
C
YCLE(1)
(A
DDRESS
C
ONTROLLED
, CS = OE = V
IL
, WE = V
IH
)
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