參數(shù)資料
型號： 2SK4206GT
廠商： PANASONIC CORP
元件分類： 小信號晶體管
英文描述： SMALL SIGNAL, FET
封裝： ROHS COMPLIANT, TSSSMINI3-F2, 3 PIN
文件頁數(shù)： 1/4頁
文件大?。?/td> 377K
代理商： 2SK4206GT
Silicon Junction FETs (Small Signal)
Publication date: August 2008
SJF00102BED
1
This product complies with the RoHS Directive (EU 2002/95/EC).
2SK4206G
Silicon N-channel junction FET
For impedance conversion in low frequency
For electret capacitor microphone
Features
Low noise voltage NV
High voltage gain GV
Thin package: TSSSMini3-F2 (1.2 mm × 1.2 mm × 0.33 mm)
Absolute Maximum Ratings Ta = 25°C
Parameter
Symbol
Rating
Unit
Drain-source voltage (Gate open)
VDSO
20
V
Drain-gate voltage (Souece open)
VDGO
20
V
Drain-source current (Gate open)
IDSO
2
mA
Drain-gate current (Souece open)
IDGO
2
mA
Power dissipation
PD
100
mW
Operating ambient temperature
Topr
–20 to +80
°
C
Storage temperature
Tstg
–55 to +125
°
C
Electrical Characteristics Ta = 25°C±3°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Drain current *1
ID
VDS = 2.0 V, Rd = 2.2 kW ± 1%
170
470
m
A
Drain-source current *2
IDSS
VDS = 2.0 V, Rd = 2.2 kW ± 1%, VGS = 0
180
450
m
A
Forward transfer conductance
Yfs
VD = 2.0 V, VGS = 0, f = 1 kHz
660
1500
m
S
Noise voltage *3
NV
VD = 2.0 V, Rd = 2.2 kW ± 1%
CO = 5 pF, A-curve
10
m
V
Voltage gain
GV1
VD = 2.0 V, Rd = 2.2 kW ± 1%
CO = 5 pF, eG = 10 mV, f = 1 kHz
–5.0
–1.0
dB
GV2
VD = 12 V, Rd = 2.2 kW ± 1%
CO = 5 pF, eG = 10 mV, f = 1 kHz
–3.0
3.0
GV3
VD = 1.5 V, Rd = 2.2 kW ± 1%
CO = 5 pF, eG = 10 mV, f = 1 kHz
–7.0
–1.5
Voltage gain difference
D
GV . f *4
VD = 2.0 V, Rd = 2.2 kW ± 1%
CO = 5 pF, eG = 10 mV
f = 1 kHz to 70 Hz
0
1.7
GV1 – GV3
0.5
2.0
dB
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.
2. A protection diode is built-in between gate and source of transistor. However if forward current ows between gate and source transistor
might be damaged. So please be careful not insert reverse.
3. *1: ID is assured for IDSS .
*2: Rank classication
Rank
T
U
ID (mA)
170 to 325
265 to 470
IDSS (mA)
180 to 305
275 to 450
*3: NV is assured for design.
*4: D|GV . f | is assured for AQL 0.065. (The measurement method is used by source-grounded circuit.)
Package
Code
TSSSMini3-F2
Pin Name
1: Drain
2: Source
3: Gate
Marking Symbol: 9H
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