參數(shù)資料
型號(hào): 2SK1794
元件分類(lèi): JFETs
英文描述: 6 A, 900 V, 2.8 ohm, N-CHANNEL, Si, POWER, MOSFET
文件頁(yè)數(shù): 9/9頁(yè)
文件大?。?/td> 403K
代理商: 2SK1794
LV5652T
Notes
(1) Soft start time setting method
The soft start time is set with the capacitor connected between CSOFT* and GND_S.
This IC has an independent soft start function for each channel, so a capacitor must be connected for each CSOFT to
set the soft start time.
(Description of soft start operation)
(Outline of soft start pin)
VREG
(Internal constant
voltage)
VB (0.515[V])
200k
Ω (RSF)
CSOFT*
4
μA (ISF)
GND_S
VB
RSF × ISF
TSOFT = CSOFT × RSFIn (
)
= 0.206
× 106 × CSOFT [s]
CSOFT* [V]
CSOFT* voltage
T [s]
VB (=0.515 [V] (TYP))
CSOFT pin charging starts
The output voltage reaches the set voltage
(Output voltage constant)
Soft start time (Tsoft [s])
(2) Setting the oscillation frequency
The internal oscillation frequency is set by the resistor connected to the RT pin and the capacitor connected to the CT
pin. The waveform generated on CT is a triangular wave with the charging/discharging waveform determined by RT
and CT.
fOSC = 1.32 Х
1
CT Х RT
[Hz]
The actual internal oscillation frequency deviates from the calculated value due to overshoot, undershoot and other
factors, so the frequency should be confirmed in an actual set.
(3) External input CLK function (CLK_IN)
Switching operation can be synchronized with external clock input (CLK_IN) by using the CLK_IN pin.
External clock (CLK_IN) frequency and input level
When using external clock (CLK_IN) input, input a frequency equal to the internal oscillation frequency +20% or
more to CLK_IN. In addition, the CLK_IN configuration is shown in the figure “CLK_IN (input) equivalent circuit
(outline)” below.
The 0.8V reference voltage and CLK_IN are compared to determine the edges, so input a signal of 0.8V or more
(VCC voltage or less) as the external clock (CLK_IN).
External/internal clock switching
Set the CTL pin Low before switching between the external clock and the internal clock. Switching clocks when
running may give rise to output voltage fluctuations.
Maximum ON duty
The maximum ON duty (Duty_MAX*) of channel 2 to channel 3 is the 85% (typ.) setting. When using the external
clock (CLK_IN), the maximum ON duty (Duty_MAX*) becomes smaller, so care must be taken for the set output
voltage.
(CLK_IN (input) equivalent circuit (outline))
CLK_IN
0.8V
No.A1512-9/9
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