參數(shù)資料
型號: 2N7002DW-7-F
廠商: DIODES INC
元件分類: 小信號晶體管
英文描述: DUAL N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR
中文描述: 115 mA, 60 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET
封裝: GREEN, ULTRA SMALL, PLASTIC PACKAGE-6
文件頁數(shù): 1/3頁
文件大?。?/td> 161K
代理商: 2N7002DW-7-F
DS30120 Rev. 8 - 2
1 of 3
2N7002DW
www.diodes.com
Diodes Incorporated
2N7002DW
DUAL N-CHANNEL ENHANCEMENT
MODE FIELD EFFECT TRANSISTOR
Features
Dual N-Channel MOSFET
Low On-Resistance
Low Gate Threshold Voltage
Low Input Capacitance
Fast Switching Speed
Low Input/Output Leakage
Ultra-Small Surface Mount Package
Lead Free/RoHS Compliant (Note 2)
Qualified to AEC-Q101 Standards for High Reliability
Maximum Ratings
@ T
A
= 25
°
C unless otherwise specified
Characteristic
Symbol
2N7002DW
Units
Drain-Source Voltage
V
DSS
60
V
Drain-Gate Voltage R
GS
1.0M
V
DGR
60
V
Gate-Source Voltage (Note 1)
Continuous
Pulsed
V
GSS
±20
±40
V
Drain Current (Note 1)
Continuous
Continuous @ 100°C
Pulsed
I
D
115
73
800
mA
Total Power Dissipation
Derating above T
A
= 25°C (Note 1)
P
d
200
1.60
mW
mW/°C
Thermal Resistance, Junction to Ambient
R
θ
JA
625
°C/W
Operating and Storage Temperature Range
T
j
, T
STG
-55 to +150
°C
A
M
J
L
D
B C
H
K
G
F
D
2
G
1
S
1
S
2
G
2
D
1
Mechanical Data
Case: SOT-363
Case Material: Molded Plastic. UL Flammability Classification
Rating 94V-0
Moisture Sensitivity: Level 1 per J-STD-020C
Terminals: Solderable per MIL-STD-202, Method 208
Lead Free Plating (Matte Tin Finish annealed over Alloy 42
leadframe).
Terminal Connections: See Diagram
Marking (See Page 2): K72
Ordering & Date Code Information: See Page 2
Weight: 0.006 grams (approx.)
SOT-363
Min
0.10
Dim
A
B
C
D
F
H
J
K
L
M
α
All Dimensions in mm
Max
0.30
1.15
1.35
2.00
2.20
0.65 Nominal
0.30
0.40
1.80
0.90
2.20
0.10
1.00
0.25
0.40
0.10
0.25
Notes:
document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.
2. No purposefully added lead.
1. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch; pad layout as shown on Diodes Inc. suggested pad layout
S
1
D
1
D
2
S
2
G
1
G
2
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