參數(shù)資料
型號(hào)： 2N5640
廠商： ON SEMICONDUCTOR
元件分類： 小信號(hào)晶體管
英文描述： 30 V, N-CHANNEL, Si, SMALL SIGNAL, JFET, TO-92
封裝： PLASTIC, TO-226AA, 3 PIN
文件頁(yè)數(shù)： 23/35頁(yè)
文件大?。?/td> 353K
代理商： 2N5640
2N5640
4–132
Motorola Small–Signal Transistors, FETs and Diodes Device Data
t f
,F
ALL
TIME
(ns)
t r
,RISE
TIME
(ns)
t d(on)
,TURN–ON
DELA
Y
TIME
(ns)
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
20
30
50
ID, DRAIN CURRENT (mA)
Figure 1. Turn–On Delay Time
RK = 0
TJ = 25°C
VGS(off) = 12 V
RK = RD′
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
20
30
50
ID, DRAIN CURRENT (mA)
Figure 2. Rise Time
RK = RD′
RK = 0
TJ = 25°C
VGS(off) = 12 V
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
20
30
50
ID, DRAIN CURRENT (mA)
Figure 3. Turn–Off Delay Time
RK = RD′
RK = 0
t d(of
f)
,TURN–OFF
DELA
Y
TIME
(ns)
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
20
30
50
ID, DRAIN CURRENT (mA)
Figure 4. Fall Time
RK = RD′
RK = 0
TYPICAL SWITCHING CHARACTERISTICS
NOTE 1
The switching characteristics shown above were measured using a
test circuit similar to Figure 5. At the beginning of the switching
interval, the gate voltage is at Gate Supply Voltage (–VGG). The
Drain–Source Voltage (VDS) is slightly lower than Drain Supply
Voltage (VDD) due to the voltage divider. Thus Reverse Transfer
Capacitance (Crss) or Gate–Drain Capacitance (Cgd) is charged to
VGG + VDS.
During the turn–on interval, Gate–Source Capacitance (Cgs)
discharges through the series combination of RGen and RK. Cgd
must discharge to VDS(on) through RG and RK in series with the
parallel combination of effective load impedance (R
′D) and
Drain–Source Resistance (rds). During the turn–off, this charge flow
is reversed.
Predicting turn–on time is somewhat difficult as the channel
resistance rds is a function of the gate–source voltage. While Cgs
discharges, VGS approaches zero and rds decreases. Since Cgd
discharges through rds, turn–on time is non–linear. During turn–off,
the situation is reversed with rds increasing as Cgd charges.
The above switching curves show two impedance conditions;
1) RK is equal to RD, which simulates the switching behavior of
cascaded stages where the driving source impedance is normally
the load impedance of the previous stage, and 2) RK = 0 (low
impedance) the driving source impedance is that of the generator.
RGEN
50
VGEN
INPUT
RK
50
RGG
VGG
50
OUTPUT
RD
+VDD
RT
SET VDS(off) = 10 V
INPUT PULSE
tr
tf
PULSE WIDTH
DUTY CYCLE
≤ 0.25 ns
≤ 0.5 ns
= 2.0
s
≤ 2.0%
RGG & RK
RD +
RD(RT
) 50)
RD ) RT ) 50
Figure 5. Switching Time Test Circuit
TJ = 25°C
VGS(off) = 12 V
TJ = 25°C
VGS(off) = 12 V
相關(guān)PDF資料
PDF描述
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